Another potential benefit of small pointers would be in page table size and intermediate page table node caching (for hierarchical and linear page tables). By avoiding a broadly distributed memory layout, fewer higher nodes would need to be cached. This reduction in sparsity could also reduce the size of the page table. (If the initial node for the application address space can be preloaded and locked in place [ARM could theoretically do this since it has a separate application page table base pointer and systems using linear page tables generally support locking TLB entries to accomplish this.], there would be no need for the higher nodes to exist.)

Less sparse page layout might also be exploited by TLBs. E.g., an L2 TLB whose entries can cache both page table nodes and page table entries could have some entries with shorter tags (a page table node uses fewer virtual address bits for the tag as would a PTE entry for a truncated address space, while both tend to use the same number of bits for the data). One might also consider extending the data field for a large page TLB entry to allow small pages in the lower address area to use such entries; with a CAM-based TLB the additional flexibility might justify the overhead. (There are probably other clever things that could be done to exploit smaller address spaces or even just compression-friendly address space use in general.)