anonymou5 (no.delete@this.spam.com) on August 14, 2012 11:03 am wrote:
> > Who uses x86 4MB pages?
>
> The use of PAE=0 is limited to scenarios in which PAE is not supported but PSE is (think
> historic x86 processors), scenarios in which PA space is less critical than the footprint
> of the page tables (the 32-bit paging entries limit 4 KiB pages to 32-bit PAs, and 4 MiB
> pages to 41-bit PAs, and they don't leave room for NX bits -- however, the tables consume
> less space), and/or scenarios in which page table walk performance matters (PDPTRs + two
> levels for PSE versus four levels for today's PAE).

I always assumed x86 large pages were used in essentially the same way BATs are used on POWER. They're not meant to be a general solution; they're a way to prevent the TLB being polluted in one particular case where this is easily avoided, namely where one has a
- large chunk of
- contiguous address space which is
- all used in the same way and which
- doesn't need to be swapped (or, unlikely, can be swapped in these large chunks)

SO two obvious use case: one might use large pages/BATs for
- covering video address space (including not just the frame buffer)
- the instruction and data footprints of the wired part of the OS.

An additional use case that sometimes arises, for dedicated machines is covering (some?) code and (some?) data that one essentially wants wired down and in constant use.
This could be the web server on some machines; the database server on some machines, perhaps even in special cases a shmem block of memory used for communication.

The point is, in ALL these cases, one knows ahead of the time what one is trying to do and why. For these uses cases, large pages work, and don't pollute the TLB. But it is fighting their design principle to assume that they are just large 4kB pages and can be handled the same way, in particular that they can usefully be AUTOMATICALLY managed by the OS --- automatically allocated, automatically swapped, automatically aggregated and de-aggregated from smaller pages.

As for 64kB pages --- bring it on. High time, and well done, ARM. Really the only thing I'd like to see in the new ISA that I don't see is
- support for multiple condition codes, like POWER
- a dedicated count register for speeding up inner loops, again like POWER.

I'm not a compiler guy, but for low level assembly hacking, multiple condition registers could be used with value. It always struck me that the compiler guys were not even trying to use them, with at least two obvious possibilities not explored:
- storing bools in conditions registers rather than standard "integer" registers
- testing conditions (when it makes sense) across basic block boundaries, rather than the paradigm of only looking within a single basic block for scheduling opportunities.

As for the dedicated count register, yes, you can get the same effect mostly with branch prediction, but this allows you to free up some of those limited branch prediction slots for more useful purposes, and gives you a register that lives close to the instruction side of the chip, not the data side, and thus a little faster when used for instruction purposes --- witness POWER's use of that register to call proc ptrs. I don't know --- maybe that sort of lack of orthogonality is just too much hassle? But count register never struck me as a bad idea, unlike some of what's in the POWER ISA.