name99 (name99.delete@this.redheron.com) on November 17, 2012 3:31 pm wrote:
[snip]
> The point is, in ALL these cases, one knows ahead of the time what one is trying to do and why.
> For these uses cases, large pages work, and don't pollute the TLB. But it is fighting their design
> principle to assume that they are just large 4kB pages and can be handled the same way, in particular
> that they can usefully be AUTOMATICALLY managed by the OS --- automatically allocated, automatically
> swapped, automatically aggregated and de-aggregated from smaller pages.

Huge pages in a hierarchical page table system can be relatively easy to de-aggregate. In addition, a TLB could take advantage of aligned page groups within a huge page that was partially de-aggregated, easily increasing peak TLB reach four fold with the addition of only 3 validity bits. (The Speculative TLB proposal also exploits such a "usually matching a huge page" characteristic by speculating that the translation will be the huge page translation.)

If memory-chip-internal copying was supported, the cost of aggregating a huge page could be significantly reduced.


> As for 64kB pages --- bring it on. High time, and well done, ARM. Really
> the only thing I'd like to see in the new ISA that I don't see is
> - support for multiple condition codes, like POWER
> - a dedicated count register for speeding up inner loops, again like POWER.

I can really sympathize; those are features that I really like. However, it is quite possible to define a GPR as a microarchitectural counter. The front-end could track the least significant bits and the number of decrements, somewhat like the stack pointer optimizations introduced to certain x86 implementations. This would allow early branch resolution (like with a specialized count register), but would not add a special purpose register to the ISA itself.

(For large loop bodies, multiple condition registers can serve a similar purpose. For short loop bodies with short iteration counts, it seems that one might actually want a count FIFO where reaching a count of zero automatically causes a move to the next entry in the buffer.)

Along similar lines, with branch on bit set/clear instructions, it would be possible to suggest a specific GPR as a microarchitectural flag register. This would be less effective than microarchitecting a count register since partial register writes would be more involved; but it might extract some of the benefit of multiple condition registers.

(Other registers may also be attractive for implementation with a future file, like global and thread-local-storage pointers.)

> I'm not a compiler guy, but for low level assembly hacking, multiple condition registers
> could be used with value. It always struck me that the compiler guys were not even
> trying to use them, with at least two obvious possibilities not explored:
> - storing bools in conditions registers rather than standard "integer" registers
> - testing conditions (when it makes sense) across basic block boundaries, rather than the
> paradigm of only looking within a single basic block for scheduling opportunities.

I agree. Another trick would be fully unrolling a short loop with small count and unrolling once its outer loop. With the four-bit condition registers in Power, the inner loop could iterate either zero to 15 times or 1 to 16 times using a different condition register for even and odd outer loop iterations. The new value for each condition register could be set at the end of its loop, allowing substantial time for the value to reach the front end. A third condition register could be set to control the outer loop.

I also wish that condition registers could be used for returning error status. While error-based branches are extremely predictable, early resolution would tend to free up resources early.

For classes with limited polymorphism (or dominated by a few cases), early setting of condition registers might be exploited to convert variable jumps into jumps using immediates. (In theory, an ISA could inline a small jump table and use a small value that would fit in a condition register to select the entry.) Multiple condition registers might be used to hold limited class information for multiple objects.

One neat aspect of multi-bit condition registers is that vector comparisons could set a result for all, one, some but not most, none.

Interestingly, Itanium has both predicate registers and a count register.

Unfortunately, front-end evaluation of condition registers seems to have fallen out of favor, perhaps in large part because of deep and wide pipelines (and OoO execution) and little (or no?) software that exploits very early setting of such values.

> As for the dedicated count register, yes, you can get the same effect mostly with branch prediction,
> but this allows you to free up some of those limited branch prediction slots for more useful purposes,
> and gives you a register that lives close to the instruction side of the chip, not the data side, and
> thus a little faster when used for instruction purposes --- witness POWER's use of that register to
> call proc ptrs. I don't know --- maybe that sort of lack of orthogonality is just too much hassle?
> But count register never struck me as a bad idea, unlike some of what's in the POWER ISA.

Itanium has branch registers specifically for earlier resolving of variable jumps.

Unfortunately, special purpose registers tend to be underutilized and constrain implementations in ways that assigning special uses to GPRs do not. A clever use of hint semantics (and possibly some special-purpose instructions using specific GPRs) might be a "better" way to allow implementations to exploit early availability and other specializations for certain cases.

Power (and Itanium) also have the disadvantage that the special purpose registers could not be loaded directly from memory or directly with an immediate value (in the case of a count) or directly from a computation.