> > > > The problem with ARM is that is an Advanced Ridiculous Instruction Set Computer Microprocessor. The RISC
> > > > started when a PhD at IBM was trying to figure out why the
> > > > code produced by the Fortran H optimizing compiler
> > > > ran faster than the same code run through the Fortran G non-optimizing compiler. It was publicized by a
> > > > college professor who used proof-by-massive-publication to tout his RISC I chip. The facts are that no
> > > > functional chip was produced. The "performance" figures compared times to run assembly code on a simulator
> > > > and then scaled by 7 to make the numbers look better vs.
> > > > high level compiled programs running on real hardware.
> > > > The RISC concept was taken to extremes by the ACM SigArch
> > > > enthusiasts who designed RISCs with only 1 instruction.
> > > > The RISC concept got high clock speeds. The problem was when you wanted to actually run programs. Reducing
> > > > the available instructions usually resulted in increasing the number instructions to perform the same task.
> > > > Windows on the SPARC was larger than Windows on the 8086. An 32-bit integer multiple takes 1 instruction
> > > > on the 8085 and 33 on the SPARC chip. I saw one "comparison" of RISC vs CISC when a SPARC chip using 5ns
> > > > RAM chips was compared to a 68000 with 250ns RAM chips.
> > > >
> > > > The engineers at ARM did a very good job of trying to produce a good RISC instruction set
> > > > by making each RISC instruction extremely complex. Look at how they multiply by 10.
> > > >
> > > > I believe that the RISC concept is why the ARM processor preforms so poorly compared to the Intel and
> > > > AMD CISC chips. You need a better architecture. I favor a stack-based direct execution architecture
> > > > like the Novix chip. Beware! The book "Stack Computers" written by a professor at CMU tries to justify
> > > > stack architecture using a chip which uses a register array to simulate a stack. At TI I worked on
> > > > a real stack computer which integrated the ALU into the top 2 stack elements and was laid out as a
> > > > 1-bit bit slice to reduce non-transistor silicon area. However, the executives at TI knew that "you
> > > > can't make money building CPUs" (ignore Intel and AMD). (Also ignore the quarterly earnings reports
> > > > that show your SBP9900 microprocessor out-selling all but one RAM chip by a factor of 10.)
> > > >
> > > > The ARM is best sold to NVIDIA to be lost into oblivion and replaced by a better architecture.
> > > >
> > > > Robert Pearson
> > >
> > > Wow. Is this 1 of April again or are these forums becoming a beacon for clinically insane?
> >
> > Or that guy was cryogenized last century, just woke up and forgot to read what happened the
> > last 15 years
>
> He's just showing what went on here years ago now that RWT is twenty five. I'm sure there's an
> awful lot we say seriously now that'll seem quite ridiculous in another ten or fifteen years ;-)

I'm sure he's just joking around. Jokes aside, if someone from the 80s got ported forward four decades, they'd say RISC is for high performance and x86 is for low power PCs. Fast forward and the situation flips. And it could flip again in the future, who knows