We previously theorized that Intel’s TSX extensions in Haswell use the caches to provide transactional memory semantics. This article describes an alternative approach based on minimal changes to the CPU core (specifically in the ROB and MOB), contrasts the advantages of the two techniques and discusses the expected implementation in Haswell.

http://www.realworldtech.com/haswell-tm-alt/

I also muse a bit about when these two techniques (cache-based and MOB-based TM) will get implemented on the roadmap and how they can work together in a very complimentary fashion.

As always comments and discussion welcome.

David