By: David Kanter (dkanter.delete@this.realworldtech.com), August 22, 2012 2:06 am
Room: Moderated Discussions
Håkan Winbom (hakan.winbom.delete@this.gmail.com) on August 22, 2012 12:52 am wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on August 21, 2012 10:17 pm
> wrote:
> > We previously theorized that Intel’s TSX extensions in Haswell
> use the caches
> > to provide transactional memory semantics. This article
> describes an alternative
> > approach based on minimal changes to the CPU core
> (specifically in the ROB and
> > MOB), contrasts the advantages of the two
> techniques and discusses the expected
> > implementation in Haswell.
> >
>
> > http://www.realworldtech.com/haswell-tm-alt/
> >
> > I
> > also
> muse a bit about when these two techniques (cache-based and MOB-based TM)
> >
> will get implemented on the roadmap and how they can work together in a very
>
> > complimentary fashion.
> >
> > As always comments and discussion
> welcome.
> >
> > David
>
> I would really like a a high level use case
> description of transactional memory.
> Do you have any good reference? Or is that
> an entirely new article?
> /HW
There are a large number of use cases. To start with, Azul's JVM used a minimal form of TM to improve garbage collection.
http://research.microsoft.com/en-us/um/people/tharris/papers/2009-ics.pdf
Hardware Lock Elision is also quite useful for handling code with locks. For example, AMD did some excellent research showing considerable benefits for memcached:
http://www.cs.purdue.edu/transact11/web/papers/Pohlack.pdf
David
> David Kanter (dkanter.delete@this.realworldtech.com) on August 21, 2012 10:17 pm
> wrote:
> > We previously theorized that Intel’s TSX extensions in Haswell
> use the caches
> > to provide transactional memory semantics. This article
> describes an alternative
> > approach based on minimal changes to the CPU core
> (specifically in the ROB and
> > MOB), contrasts the advantages of the two
> techniques and discusses the expected
> > implementation in Haswell.
> >
>
> > http://www.realworldtech.com/haswell-tm-alt/
> >
> > I
> > also
> muse a bit about when these two techniques (cache-based and MOB-based TM)
> >
> will get implemented on the roadmap and how they can work together in a very
>
> > complimentary fashion.
> >
> > As always comments and discussion
> welcome.
> >
> > David
>
> I would really like a a high level use case
> description of transactional memory.
> Do you have any good reference? Or is that
> an entirely new article?
> /HW
There are a large number of use cases. To start with, Azul's JVM used a minimal form of TM to improve garbage collection.
http://research.microsoft.com/en-us/um/people/tharris/papers/2009-ics.pdf
Hardware Lock Elision is also quite useful for handling code with locks. For example, AMD did some excellent research showing considerable benefits for memcached:
http://www.cs.purdue.edu/transact11/web/papers/Pohlack.pdf
David
Topic | Posted By | Date |
---|---|---|
Article: Haswell TM Alternatives | David Kanter | 2012/08/21 10:17 PM |
Article: Haswell TM Alternatives | Håkan Winbom | 2012/08/22 12:52 AM |
Article: Haswell TM Alternatives | David Kanter | 2012/08/22 02:06 AM |
Article: Haswell TM Alternatives | anon | 2012/08/22 09:46 AM |
Article: Haswell TM Alternatives | Linus Torvalds | 2012/08/22 10:16 AM |
Article: Haswell TM Alternatives | Doug S | 2012/08/24 09:34 AM |
AMD's ASF even more limited | Paul A. Clayton | 2012/08/22 10:20 AM |
AMD's ASF even more limited | Linus Torvalds | 2012/08/22 10:41 AM |
Compiler use of ll/sc? | Paul A. Clayton | 2012/08/28 10:28 AM |
Compiler use of ll/sc? | Linus Torvalds | 2012/09/08 01:58 PM |
Lock recognition? | Paul A. Clayton | 2012/09/10 02:17 PM |
Sorry, I was confused | Paul A. Clayton | 2012/09/13 11:56 AM |
Filter to detect store conflicts | Paul A. Clayton | 2012/08/22 10:19 AM |
Article: Haswell TM Alternatives | bakaneko | 2012/08/22 03:02 PM |
Article: Haswell TM Alternatives | David Kanter | 2012/08/22 03:45 PM |
Article: Haswell TM Alternatives | bakaneko | 2012/08/22 10:56 PM |
Cache line granularity? | Paul A. Clayton | 2012/08/28 10:28 AM |
Cache line granularity? | David Kanter | 2012/08/31 09:13 AM |
A looser definition might have advantages | Paul A. Clayton | 2012/09/01 07:29 AM |
Cache line granularity? | rwessel | 2012/08/31 08:54 PM |
Alpha load locked granularity | Paul A. Clayton | 2012/09/01 07:29 AM |
Alpha load locked granularity | anon | 2012/09/02 06:23 PM |
Alpha pages groups | Paul A. Clayton | 2012/09/03 05:16 AM |
An alternative implementation | Maynard Handley | 2012/11/20 10:52 PM |
An alternative implementation | bakaneko | 2012/11/21 06:52 AM |
Guarding unread values? | Paul A. Clayton | 2012/11/21 09:39 AM |
Guarding unread values? | bakaneko | 2012/11/21 12:25 PM |
TM granularity and versioning | Paul A. Clayton | 2012/11/21 09:27 AM |
TM granularity and versioning | Maynard Handley | 2012/11/21 11:52 AM |
Indeed, TM (and coherence) has devilish details (NT) | Paul A. Clayton | 2012/11/21 11:56 AM |