Håkan Winbom (hakan.winbom.delete@this.gmail.com) on August 22, 2012 12:52 am wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on August 21, 2012 10:17 pm
> wrote:
> > We previously theorized that Intel’s TSX extensions in Haswell
> use the caches
> > to provide transactional memory semantics. This article
> describes an alternative
> > approach based on minimal changes to the CPU core
> (specifically in the ROB and
> > MOB), contrasts the advantages of the two
> techniques and discusses the expected
> > implementation in Haswell.
> >
>
> > http://www.realworldtech.com/haswell-tm-alt/
> >
> > I
> > also
> muse a bit about when these two techniques (cache-based and MOB-based TM)
> >
> will get implemented on the roadmap and how they can work together in a very
>
> > complimentary fashion.
> >
> > As always comments and discussion
> welcome.
> >
> > David
>
> I would really like a a high level use case
> description of transactional memory.
> Do you have any good reference? Or is that
> an entirely new article?
> /HW

There are a large number of use cases. To start with, Azul's JVM used a minimal form of TM to improve garbage collection.

http://research.microsoft.com/en-us/um/people/tharris/papers/2009-ics.pdf

Hardware Lock Elision is also quite useful for handling code with locks. For example, AMD did some excellent research showing considerable benefits for memcached:

http://www.cs.purdue.edu/transact11/web/papers/Pohlack.pdf

David