David Kanter (dkanter.delete@this.realworldtech.com) on August 21, 2012 10:17 pm wrote:
> We previously theorized that Intel’s TSX extensions in Haswell use the caches
> to provide transactional memory semantics. This article describes an alternative
> approach based on minimal changes to the CPU core (specifically in the ROB and
> MOB), contrasts the advantages of the two techniques and discusses the expected
> implementation in Haswell.
>
> http://www.realworldtech.com/haswell-tm-alt/
>
> I
> also muse a bit about when these two techniques (cache-based and MOB-based TM)
> will get implemented on the roadmap and how they can work together in a very
> complimentary fashion.
>
> As always comments and discussion welcome.
>
> David

Mhm, I don't get what is so important here. The question
where to keep the old and new values (L2, L1D, MOB, other
buffers) comes from the microarchitecture. So the old values
into L2 of the core with the transaction and the new values
into the L1D/MOB/local buffer, depending on the amount of
expected data beyond what can be kept back in the MOB.

I don't understand how the MOB would have to do more in such
a scenario, and I don't see how important pushing everything
into the MOB is in the first place. That's at least my naive
technical opinion forgetting all the little details.

But there are other problems: I can't measure transactions.
How will changes in the microarchitecture change the
behaviour of programs which use them outside the transaction
size?

And how long-lived are transactions in sight of more
cooperative mechanisms? Threads which work on the same
memory always cooperate, so models which support better
cooperation are necessary anyway. (Not that I know any.)