Paul A. Clayton (paaronclayton.delete@this.gmail.com) on September 1, 2012 7:29 am wrote:
> rwessel (robertwessel.delete@this.yahoo.com) on August 31, 2012 8:54 pm
> wrote:
> > Paul A. Clayton (paaronclayton.delete@this.gmail.com) on
> >
> August 28, 2012 10:28 am wrote:
> [snip]
> >> (The Alpha architectural
> suggestion for portability of not
> >> placing two atomic operands within
> the same 8 KiB page seems
> >> a bit excessive.)
> [snip]
> > While it
> might have been changed subsequently, the original
> > Alpha architectural
> suggestion was that such items be quadword
> > aligned and in their own
> "large cache block", which were defined as "likely
> > be(ing) 32, 64, 128 or
> 256 bytes".
>
> I seem to have misinterpreted a statement in version 4 (1998) of
> the Alpha Architecture Handbook--"A processor’s locked range is the aligned
> block of 2**N bytes that includes the locked_physical_address. The 2**N value is
> implementation dependent. It is at least 16 (minimum lock range is an aligned
> 16-byte block) and is at most the page size for that implementation (maximum
> lock range is one physical
> page)."--and did not remember another statement just
> a page later--"Hardware implementations are encouraged to lock no more than 128
> bytes. Software implementations are encouraged to separate locked locations by
> at least 128 bytes from
> other locations that could potentially be written by
> another processor while the first location is locked."
>
> It seems Alpha did
> settle on a single "recommended" number, though I think allowing for page-sized
> granularity might be excessive. (An implementation could--at some complexity
> cost--still use primarily page-sized coherence while supporting a finer
> granularity for LLDx_L/STx_C, though 8KiB seems excessively large for the common
> coherence granularity.)
>
> (Of course, Alpha did eventually support 64 KiB base
> pages.)

Didn't Alpha always support 64 KB, in addition to 8 KB, 512 KB, and 2 MB page sizes?