By: Maynard Handley (name99.delete@this.redheron.com), November 21, 2012 11:52 am
Room: Moderated Discussions
Paul A. Clayton (paaronclayton.delete@this.gmail.com) on November 21, 2012 9:27 am wrote:
> Maynard Handley (name99.delete@this.redheron.com) on November 20, 2012 10:52 pm wrote:
> > "Intel’s TSX tracks the read-set and write-set at cache line (64B) granularity during a transaction.
> > An RS conflict occurs if a cache line in the read-set is written by another thread."
> >
> > Is it really necessary to do things this way?
My apologies. I started writing a piece to explain my point in more careful detail, but realized as I became more specific that while it would work in the most common cases, it could fail in more sophisticated situations --- which renders the whole idea moot.
Well, c'est la vie.
> Maynard Handley (name99.delete@this.redheron.com) on November 20, 2012 10:52 pm wrote:
> > "Intel’s TSX tracks the read-set and write-set at cache line (64B) granularity during a transaction.
> > An RS conflict occurs if a cache line in the read-set is written by another thread."
> >
> > Is it really necessary to do things this way?
My apologies. I started writing a piece to explain my point in more careful detail, but realized as I became more specific that while it would work in the most common cases, it could fail in more sophisticated situations --- which renders the whole idea moot.
Well, c'est la vie.
| Topic | Posted By | Date |
|---|---|---|
| Article: Haswell TM Alternatives | David Kanter | 2012/08/21 10:17 PM |
| Article: Haswell TM Alternatives | Håkan Winbom | 2012/08/22 12:52 AM |
| Article: Haswell TM Alternatives | David Kanter | 2012/08/22 02:06 AM |
| Article: Haswell TM Alternatives | anon | 2012/08/22 09:46 AM |
| Article: Haswell TM Alternatives | Linus Torvalds | 2012/08/22 10:16 AM |
| Article: Haswell TM Alternatives | Doug S | 2012/08/24 09:34 AM |
| AMD's ASF even more limited | Paul A. Clayton | 2012/08/22 10:20 AM |
| AMD's ASF even more limited | Linus Torvalds | 2012/08/22 10:41 AM |
| Compiler use of ll/sc? | Paul A. Clayton | 2012/08/28 10:28 AM |
| Compiler use of ll/sc? | Linus Torvalds | 2012/09/08 01:58 PM |
| Lock recognition? | Paul A. Clayton | 2012/09/10 02:17 PM |
| Sorry, I was confused | Paul A. Clayton | 2012/09/13 11:56 AM |
| Filter to detect store conflicts | Paul A. Clayton | 2012/08/22 10:19 AM |
| Article: Haswell TM Alternatives | bakaneko | 2012/08/22 03:02 PM |
| Article: Haswell TM Alternatives | David Kanter | 2012/08/22 03:45 PM |
| Article: Haswell TM Alternatives | bakaneko | 2012/08/22 10:56 PM |
| Cache line granularity? | Paul A. Clayton | 2012/08/28 10:28 AM |
| Cache line granularity? | David Kanter | 2012/08/31 09:13 AM |
| A looser definition might have advantages | Paul A. Clayton | 2012/09/01 07:29 AM |
| Cache line granularity? | rwessel | 2012/08/31 08:54 PM |
| Alpha load locked granularity | Paul A. Clayton | 2012/09/01 07:29 AM |
| Alpha load locked granularity | anon | 2012/09/02 06:23 PM |
| Alpha pages groups | Paul A. Clayton | 2012/09/03 05:16 AM |
| An alternative implementation | Maynard Handley | 2012/11/20 10:52 PM |
| An alternative implementation | bakaneko | 2012/11/21 06:52 AM |
| Guarding unread values? | Paul A. Clayton | 2012/11/21 09:39 AM |
| Guarding unread values? | bakaneko | 2012/11/21 12:25 PM |
| TM granularity and versioning | Paul A. Clayton | 2012/11/21 09:27 AM |
| TM granularity and versioning | Maynard Handley | 2012/11/21 11:52 AM |
| Indeed, TM (and coherence) has devilish details (NT) | Paul A. Clayton | 2012/11/21 11:56 AM |