Latency and HPC Workloads

Article: Intel's Near-Threshold Voltage Computing and Applications
By: Michael S (already5chosen.delete@this.yahoo.com), October 8, 2012 5:12 pm
Room: Moderated Discussions
SHK (nomail.delete@this.mail.com) on October 8, 2012 2:42 pm wrote:
> [snip]
>

> First, you will have to convince Intel/AMD to include
> support for
> RLDRAM into their IMCs. According to my understanding, RLDRAM access
> protocol
> is substantially different from SDRAM DDR2/DDR3, or any SDRAM for that
> matter,
> so the required effort is not trivial.
>

>
> Sure, but i was talking about the
> higher end of the performance scale, not commodity systems. Something like the
> big POWER systems,

Big POWER systems use fully-buffered memories. So, latency wouldn't be as good as commodity boxen regardless of interface you use between buffer and memory device.
Besides, I don't know we they do the scheduling, in the controller, i.e in Power chip or in the buffer itself. If the former, then you face the same problem as with Intel/AMD.

> BlueGene

For previous generations of BlueGene RLDRAM looks like a nice fit. But current generation packs quite a few cores in a single die, so they, too, are starting to want state-of-the-art capacity per pin.

> or a vector system like the NEC's SX-series. IIRC
> the SX-6 was available either in a "high capacity" DRAM version or "low latency"
> FCRAM main memory. Dunno if SX-9 or future NEC systems will have the same config
> option.
>
>

> Second, RLDRAM would be pretty
> bad for capacity, except if your
> opt for some form of fully buffered, which by
> itself adds more latency than
> RLDRAM saves.
> If I am not mistaken, with RLDRAM you can't currently get more
> than 512 MB per 64bit "channel". That's like going almost full decade back.
> With standard unbuffered DDR3 you can easily get 8 GB per channel, with
> registered DDR3 - up to 96 GB/channel.
>

>
> On micron.com RLDRAM3 is marked as
> 576Mbit density vs 8Gbit of commodity DDR3 which is kinda disappointing.

And that's only 1/3rd of the problem.
Another one is absence of x8 and x4 parts.
And third one is the # of supported ranks on the same data bus. If I am not mistaken, RLDRAM only supports 2 ranks per data bus. DDR3 supports 4 ranks on the same bus with no rate compromises. With slower rate - quite a few more. I don't know how much exactly. Something like 12?

> Is the
> tradeoff capacity vs latency inevitabile like in caches?

It sounds that way.

> Maybe switching to a
> FLASH+RLDRAM (o similar) would be a better compromise?

Per chip, flash is ~ two orders of magnitude away from SDRAM in write bandwidth. And when you start to aggregate many chips on the same bus to improve write bandwidth, you inevitably hurt read latency in the process. And, BTW, for NAND flash read latency is pretty bad to start with. As to NOR flash, assuming it serves as 2-nd level storage behid few GBs of RLDRAM "cache", its read latency is good enough, but write bandwidth is pretty horrible, even by comparison to NAND flash. Besides, right now NOR flash faces major difficulties with scaling to finer silicon geometries.
"Or similar" sounds good, but so far the most promising technologies (PCRAM and MRAM) did not deliver - the former on write bandwidth, the later on density.

>
> I'm asking because i
> remember papers from more than 10 years ago on the "memory and power wall" but,
>
> while there have been a lot of power efficency improvements, the memory wall
> keeps getting worse,
> and larger caches, prefetch and all that (IMHO!) seems
> only a palliative solution to the fundamental
> problem of redesigning a more
> balanced memory-ALU interconnection.
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TopicPosted ByDate
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