By: forestlaughing (forestlaughing.delete@this.yahoo.com), October 15, 2012 9:21 am
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on October 15, 2012 8:55 am wrote:
> The original context was Micron RLDRAM
Well, I think the cost issue remains true. Capacity is just too low for most users of the power architecture, so IBM isn't going to go all-in on RLDRAM. Ideally, one would have a memory interface that could accept either type of memory, letting the user chose whether latency or capacity are most important, though it sounds like RLDRAM is different enough from SDRAM that such isn't possible.
For what it's worth, IBM's L3 cache is Dram, not SRAM. I think low latency memories have a chance if they help the common case user, which caches, and the like, generally do.
> The original context was Micron RLDRAM
Well, I think the cost issue remains true. Capacity is just too low for most users of the power architecture, so IBM isn't going to go all-in on RLDRAM. Ideally, one would have a memory interface that could accept either type of memory, letting the user chose whether latency or capacity are most important, though it sounds like RLDRAM is different enough from SDRAM that such isn't possible.
For what it's worth, IBM's L3 cache is Dram, not SRAM. I think low latency memories have a chance if they help the common case user, which caches, and the like, generally do.
