By: none (none.delete@this.none.com), February 1, 2013 1:13 pm
Room: Moderated Discussions
Richard Cownie (tich.delete@this.pobox.com) on February 1, 2013 12:32 pm wrote:
[...]
> I'm familiar with Mentor's Veloce/Veloce2 fpga-based emulation system - it solves the
> timing-modelling issues and multi-fpga partitioning that you mention, and gives
> a bunch of other useful functionality as well (e.g. visibility of all signals) - but
> costs a lot more than fpga-prototyping boards, and typically runs the
> emulated user clock at < 2MHz. It gets used a lot for SoC developments.
Cadence PXP is about the same.
[...]
> I'm familiar with Mentor's Veloce/Veloce2 fpga-based emulation system - it solves the
> timing-modelling issues and multi-fpga partitioning that you mention, and gives
> a bunch of other useful functionality as well (e.g. visibility of all signals) - but
> costs a lot more than fpga-prototyping boards, and typically runs the
> emulated user clock at < 2MHz. It gets used a lot for SoC developments.
Cadence PXP is about the same.