By: anon (anon.delete@this.anon.com), February 3, 2013 6:08 pm
Room: Moderated Discussions
Patrick Chase (patrickjchase.delete@this.gmail.com) on February 3, 2013 3:35 pm wrote:
> anon (anon.delete@this.anon.com) on February 3, 2013 2:58 pm wrote:
> > > R10K was 307 mm^2 in for core + L1s, PPro was 198 mm^2 for the same,
> > > both in 0.35 um. PPro was ~1/3 smaller, period, end of discussion.
> >
> > I would not say that is the only thing that matters, if you make a statement like "x86 penalty is trivial".
>
> David's article addressed the area penalty for x86, and that was the context of my subsequent
> reply in this forum. Given that context, area is indeed the only thing that matters (provided
> the processes are equivalent - As I noted previously, I think Intel actually had the edge
> at that point. 0.35um BiCMOS and 0.35um CMOS are not the same thing).
>
> You should of course start a new discussion with a different context of your choice, or separately reply to
> David and explain why his metric is bogus (though he already acknowledged its limitations in his article).
>
> FWIW, I have a dim recollection of an Email or USENET post from Bob Colwell (chief architect of P6) where
> he gave his estimate of how much he "paid" for x86 - He estimated 1 million gates out of 5.5. So by his
> estimate P6 was slightly above the 15% mark. I'd still argue (as Bob did at the time) that that falls into
> the "trivial" range in that it won't realistically be a significant factor in purchasing decisions.
From your initial post I replied to, you wrote:
> I think that the statement that x86 takes 5-15% more area than RISC is a bit simplistic,
> because the penalty is highly variable depending on what performance level you're
> targeting and what sort of microarchitecture you have to use to get there.
>
> As a simple example, x86 is utterly noncompetitive at the area/performance/power levels of, say, a Cortex
> M1/M3/M4 or even an R4.
[...]
> The "x86 penalty" becomes fairly trivial once you get
> up to full-blown out-of-order Tomasulo machines and the like.
So you seemed to be implying that at P6 level, x86 penalty was much smaller.
And I do not agree that 15% is trivial, but not interested in simply arguing semantics. 15% could be enough to significantly counter a process advantage, for example.
> anon (anon.delete@this.anon.com) on February 3, 2013 2:58 pm wrote:
> > > R10K was 307 mm^2 in for core + L1s, PPro was 198 mm^2 for the same,
> > > both in 0.35 um. PPro was ~1/3 smaller, period, end of discussion.
> >
> > I would not say that is the only thing that matters, if you make a statement like "x86 penalty is trivial".
>
> David's article addressed the area penalty for x86, and that was the context of my subsequent
> reply in this forum. Given that context, area is indeed the only thing that matters (provided
> the processes are equivalent - As I noted previously, I think Intel actually had the edge
> at that point. 0.35um BiCMOS and 0.35um CMOS are not the same thing).
>
> You should of course start a new discussion with a different context of your choice, or separately reply to
> David and explain why his metric is bogus (though he already acknowledged its limitations in his article).
>
> FWIW, I have a dim recollection of an Email or USENET post from Bob Colwell (chief architect of P6) where
> he gave his estimate of how much he "paid" for x86 - He estimated 1 million gates out of 5.5. So by his
> estimate P6 was slightly above the 15% mark. I'd still argue (as Bob did at the time) that that falls into
> the "trivial" range in that it won't realistically be a significant factor in purchasing decisions.
From your initial post I replied to, you wrote:
> I think that the statement that x86 takes 5-15% more area than RISC is a bit simplistic,
> because the penalty is highly variable depending on what performance level you're
> targeting and what sort of microarchitecture you have to use to get there.
>
> As a simple example, x86 is utterly noncompetitive at the area/performance/power levels of, say, a Cortex
> M1/M3/M4 or even an R4.
[...]
> The "x86 penalty" becomes fairly trivial once you get
> up to full-blown out-of-order Tomasulo machines and the like.
So you seemed to be implying that at P6 level, x86 penalty was much smaller.
And I do not agree that 15% is trivial, but not interested in simply arguing semantics. 15% could be enough to significantly counter a process advantage, for example.
