anon (anon.delete@this.anon.com) on February 3, 2013 6:08 pm wrote:> From your initial post I replied to, you wrote:
>
> > I think that the statement that x86 takes 5-15% more area than RISC is a bit simplistic,
> > because the penalty is highly variable depending on what performance level you're
> > targeting and what sort of microarchitecture you have to use to get there.
> >
> > As a simple example, x86 is utterly noncompetitive at the area/performance/power levels of, say, a Cortex
> > M1/M3/M4 or even an R4.
> [...]
> > The "x86 penalty" becomes fairly trivial once you get
> > up to full-blown out-of-order Tomasulo machines and the like.
>
> So you seemed to be implying that at P6 level, x86 penalty was much smaller.

I was implying that the penalty was vastly smaller than it is in the two cases (R3000 parity, A8 parity) that I had addressed in the previous paragraph. I believe I said "nontrivial integer factors" (i.e. hundreds of percent) in the area/performance regime where the RISCs would employ a classic 5-stage pipe, so clearly I was arguing that David's estimate was *low* by an order of magnitude in that case.

In this sort of thing a 5-15% area difference really is low enough that other factors (ecosystem etc) dominate. That makes it a practically trivial difference. The obvious exception would be the case where most of the other factors are neutralized, for example AMD vs Intel.

-- Patrick