By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), February 3, 2013 9:40 pm
Room: Moderated Discussions
Patrick Chase (patrickjchase.delete@this.gmail.com) on February 3, 2013 7:40 pm wrote:
> anon (anon.delete@this.anon.com) on February 3, 2013 6:11 pm wrote:
[snip]
> This isn't a cleanliness issue, but a page size greater than 64 KB would be
> nice for some applications with particularly TLB-hostile access patterns.
"Technology Preview: The ARMv8 Architecture" only mentions: "AArch64 also now natively supports a 64KB minimum page size". It does not indicate they they dropped support for directory node page size (1MiB in ARMv7, IIRC). AArch64 appears to use the x86-style hierarchy of having each level of the page table use the base size page, so supporting node page sizes would provide 2MiB pages [with 4KiB base pages; 1GiB for second level] or 512MiB [with 64KiB base pages]--eep! It is also quite possible that 64KiB pages will be supported with 4KiB base pages (as in ARMv7, IIRC) and perhaps 1 or 2 MiB pages with 64KiB base pages. It is also possible that every 4x multiple of the base page size will be supported (like the MIPS TLB, and mostly Itanium [it added 8KiB and excluded, it seems, 1GiB]--the Alpha 21264 TLB use 8x multiple).
Given that some implementations will include support for the 32-bit ISA, support for something close to its 1MiB pages seems likely.
Or do you have not yet public information that indicates that only 4KiB and 64KiB pages will be supported?
> anon (anon.delete@this.anon.com) on February 3, 2013 6:11 pm wrote:
[snip]
> This isn't a cleanliness issue, but a page size greater than 64 KB would be
> nice for some applications with particularly TLB-hostile access patterns.
"Technology Preview: The ARMv8 Architecture" only mentions: "AArch64 also now natively supports a 64KB minimum page size". It does not indicate they they dropped support for directory node page size (1MiB in ARMv7, IIRC). AArch64 appears to use the x86-style hierarchy of having each level of the page table use the base size page, so supporting node page sizes would provide 2MiB pages [with 4KiB base pages; 1GiB for second level] or 512MiB [with 64KiB base pages]--eep! It is also quite possible that 64KiB pages will be supported with 4KiB base pages (as in ARMv7, IIRC) and perhaps 1 or 2 MiB pages with 64KiB base pages. It is also possible that every 4x multiple of the base page size will be supported (like the MIPS TLB, and mostly Itanium [it added 8KiB and excluded, it seems, 1GiB]--the Alpha 21264 TLB use 8x multiple).
Given that some implementations will include support for the 32-bit ISA, support for something close to its 1MiB pages seems likely.
Or do you have not yet public information that indicates that only 4KiB and 64KiB pages will be supported?
