Paul A. Clayton (paaronclayton.delete@this.gmail.com) on February 3, 2013 9:40 pm wrote:
> Patrick Chase (patrickjchase.delete@this.gmail.com) on February 3, 2013 7:40 pm wrote:
> > anon (anon.delete@this.anon.com) on February 3, 2013 6:11 pm wrote:
> [snip]
> > This isn't a cleanliness issue, but a page size greater than 64 KB would be
> > nice for some applications with particularly TLB-hostile access patterns.
>
> "Technology Preview: The ARMv8 Architecture" only mentions: "AArch64 also now natively supports a 64KB minimum
> page size". It does not indicate they they dropped support for directory node page size (1MiB in ARMv7,
> IIRC). AArch64 appears to use the x86-style hierarchy of having each level of the page table use the base
> size page, so supporting node page sizes would provide 2MiB pages [with 4KiB base pages; 1GiB for second
> level] or 512MiB [with 64KiB base pages]--eep! It is also quite possible that 64KiB pages will be supported
> with 4KiB base pages (as in ARMv7, IIRC) and perhaps 1 or 2 MiB pages with 64KiB base pages. It is also
> possible that every 4x multiple of the base page size will be supported (like the MIPS TLB, and mostly Itanium
> [it added 8KiB and excluded, it seems, 1GiB]--the Alpha 21264 TLB use 8x multiple).
>
> Given that some implementations will include support for the 32-bit
> ISA, support for something close to its 1MiB pages seems likely.
>
> Or do you have not yet public information that indicates that only 4KiB and 64KiB pages will be supported?

It appears likely that you know more than I here.

I've done most of my work with ARM CPUs on OSes that don't exploit large TLB entries, so I don't have direct practical experience as I do with, say, x86. I read through ARM's public white-papers [*] and couldn't find any reference to TLB entries >64KB, but I probably simply missed something. I just read through again with your comment in mind, and I *still* don't see anything relevant, though, except for the use of the expression "minimum page size". It seems to be a curious omission for an architecture that's being touted as a potential *server* platform...

The page tables are indeed 9 bits/level for 4 KB pages and 13 bits/level for 64. A 512 MiB PTE would still be useful for things like the OSes 1:1 view of the physical address space.

[*] I have access to more information, but it would be subject to NDA and so I'd have to shut up. I haven't looked as I haven't needed to :-)