> > Well to start with, let's just avoid the word "trivial". If you say it was 15% for the P6. Then would that mean
> > similar difference for CPUs competing in today's 3-issue medium-depth (A15 class) performance range? In that
> > case, for the ARM market share I think 15% is a very big difference. If you could make the CPUs for 15% cheaper
> > than competitor, you would take their market (or have much higher margins at the same market share).

Patrick's point, which I agree with, is that the x86 penalty really depends a lot on context. I think that for a scalar core, it's probably more than 15%. But for something like the P3, it's a lot less. That's doubly true once you start talking about caches in the range of 1MB/core. At that point, the x86 penalty is really quite small.

And it's a fair point, but one I didn't want to dive into because of the inherent complexity. But it's true, the x86 overhead depends on the performance of the core; the higher performance the lower the overhead.

David