By: Etienne (etienne_lorrain.delete@this.yahoo.fr), February 5, 2013 6:57 am
Room: Moderated Discussions
Jouni Osmala (josmala.delete@this.cc.hut.fi) on February 4, 2013 11:15 pm wrote:
> Almost decade ago I defined architecture with instead of mask it counted the skips and
> nullified. What I figured out during the exercise that register renaming becomes a
> problematic with this kind of instructions.
> I think the conditional move instruction brings most of the benefits with far
> less problems.
I fail to understand the problem, care to provide an example?
Why is it incompatible with register renaming? Rename what I call "NOP" with
a "conditional move" where you know the condition is false and that would
release the entry in the physical register file.
The problem of the condition bits of the flag register is that they may have
an effect a long time after the "test/add" instruction, and that may delay the
retirement of other instructions - but in practice most condition bits are used
just few instructions after they are calculated (if they are ever used).
With the system I describe (I am not a processor designer), you do not get rid
of the flags register because you still have to store the interrupt enable bit,
and the NOPify mask in case of exception/interrupt, but you decide which instruction
to execute and which to NOPify very early, you get rid of status flag dependencies.
Obviously then the "add with carry" becomes a bit more complex because that will
involve a possibly NOPified increment, but isn't that simpler than managing bits
which may or may not have an effect later on?
Etienne.
> Almost decade ago I defined architecture with instead of mask it counted the skips and
> nullified. What I figured out during the exercise that register renaming becomes a
> problematic with this kind of instructions.
> I think the conditional move instruction brings most of the benefits with far
> less problems.
I fail to understand the problem, care to provide an example?
Why is it incompatible with register renaming? Rename what I call "NOP" with
a "conditional move" where you know the condition is false and that would
release the entry in the physical register file.
The problem of the condition bits of the flag register is that they may have
an effect a long time after the "test/add" instruction, and that may delay the
retirement of other instructions - but in practice most condition bits are used
just few instructions after they are calculated (if they are ever used).
With the system I describe (I am not a processor designer), you do not get rid
of the flags register because you still have to store the interrupt enable bit,
and the NOPify mask in case of exception/interrupt, but you decide which instruction
to execute and which to NOPify very early, you get rid of status flag dependencies.
Obviously then the "add with carry" becomes a bit more complex because that will
involve a possibly NOPified increment, but isn't that simpler than managing bits
which may or may not have an effect later on?
Etienne.