Seni (seniike.delete@this.hotmail.com) on February 14, 2013 7:45 am wrote:
> Maynard Handley (name99.delete@this.redheron.com) on February 13, 2013 3:53 pm wrote:
> > anon (anon.delete@this.anon.com) on February 3, 2013 10:06 pm wrote:
> > > Patrick Chase (patrickjchase.delete@this.gmail.com) on February 3, 2013 7:40 pm wrote:
> > > > anon (anon.delete@this.anon.com) on February 3, 2013 6:11 pm wrote:
> > > > > Patrick Chase (patrickjchase.delete@this.gmail.com) on February 3, 2013 4:29 pm wrote:
> > > > > > Paul A. Clayton (paaronclayton.delete@this.gmail.com) on February 2, 2013 11:10 am wrote:
> > > > >
> > > > > > > A clean RISC like Alpha (or--from what I have read--AArch64) would be much more friendly to fast bring-up
> > > > > > > of a decent microarchitecture. (Classic ARM seems to be somewhere in the middle--not as complex as x86 but
> > > > > > > not as simple as Alpha--, but even with Thumb2+classic ARM it might be closer to Alpha than to x86.)
> > > > > >
> > > > > > AArch64 is indeed a nice, classic RISC architecture. In particular they fixed the biggest
> > > > > > single limitation of classic ARM (spending instruction encoding bits on condition-based
> > > > > > predication at the expense of GPRs). I'd put it somewhere between MIPS and Alpha on
> > > > > > the "architectural purity scale", and that's a pretty good place to be.
> > > > >
> > > > > What are some aspects of the ISA that make it less clean than Alpha, would you say?
> > >
> > > Thanks for the answer.
> > >
> > > >
> > > > Continued reliance on condition flags.
> > >
> > > What is cleaner? GPR for comparison/branch?
> >
> > The right solution is what it has always been --- the PPC/POWER solution.
> > (a) Multiple condition registers.
> > (b) Most instructions come in two variants, one of which sets conditions, one of which does not.
> > (c) Compares can choose which condition register to modify.
> >
> > I'd be willing to give up (b) (so that no instructions except cpmpares modify the condition
> > registers) if it's considered too much hassle (eg has to be cracked into micro-ops) but
> > it is really convenient and helps quite a bit with instruction bandwidth.
> >
> > I'd also add one thing which wasn't in original POWER/PPC which is predicated moves.
> > I can live without general predication, but a predicated move from registerA to
> > registerB is SO convenient and saves so many stupid little pipeline bubbles.
>
> the CLEANEST solution is the one where none of the mess is exposed.
> Flags and condition registers are nothing but mess.
> The compare and branch should be done together in the same
> intruction and the intermediate results never stored.
>
> Like this:
>
> JL - Jump if Less
>
> JL dest, reg1, reg2
>
> Jumps to displacement dest if value in reg1 is less than value in reg2
>
>
> So you don't need a second register file just for condition registers, nor special mov
> instructions to touch that register file, nor a special renamer for it. You also reduce
> the number of instructions to be executed by one per branch, and eliminate two expensive
> register file accesses - one to write the condition code and one to read it back.
>
> This is clean. It is also efficient, which is why x86 has been doing compare+branch fusion since Conroe.


As I mentioned elsewhere in this thread, compare-and-branch is an excellent choice, but I'd really also want something to do a compare without a branch. You want to be able to combine some simple tests without a branch, and to do some limited predication. Not always, but there are definitely times to want those. Compare-and-set-GPR seems like a better choice there than actual CCs.