By: EduardoS (no.delete@this.spam.com), February 15, 2013 10:45 am
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on February 15, 2013 2:28 am wrote:
> Since it's been used only in relatively low-performance cores I don't know how it would scale to a wide, deeply
> pipelined OoOE engine but I don't see any major drawbacks. I think that having basically only one register and
> a handful of instructions that can peek and poke at it should make it easy to aggressively rename it.
I have no idea of how the flags register is renamed on those "clean" archs, if I had to I would just add one bit to every register to hold the flag to keep a single register output per operation.
> Since it's been used only in relatively low-performance cores I don't know how it would scale to a wide, deeply
> pipelined OoOE engine but I don't see any major drawbacks. I think that having basically only one register and
> a handful of instructions that can peek and poke at it should make it easy to aggressively rename it.
I have no idea of how the flags register is renamed on those "clean" archs, if I had to I would just add one bit to every register to hold the flag to keep a single register output per operation.
