By: Max (max.delete@this.a.com), February 15, 2013 1:24 pm
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on February 15, 2013 2:28 am wrote:
> Linus Torvalds (torvalds.delete@this.linux-foundation.org) on February 14, 2013 4:44 pm wrote:
> > And putting the condition codes in GPRs (alpha) may look really
> > clean and allows some nice combined conditionals,
> > but the upside just isn't there. It doesn't really generate better code: you win some, you lose some.
>
> Due to the very compact instruction encoding SuperH processors use a system which is probably the "cleanest"
> I've seen: they have a single-bit flag register (T register) which is implicitly set by comparison
> operations and read by conditional branch instructions.
Motorola MCORE did that also, for the same reason (only 16-bit instructions, and with a single bit flag the branch displacement is enlarged by 3 bits, e.g. from 8 to 11).
Max
> Linus Torvalds (torvalds.delete@this.linux-foundation.org) on February 14, 2013 4:44 pm wrote:
> > And putting the condition codes in GPRs (alpha) may look really
> > clean and allows some nice combined conditionals,
> > but the upside just isn't there. It doesn't really generate better code: you win some, you lose some.
>
> Due to the very compact instruction encoding SuperH processors use a system which is probably the "cleanest"
> I've seen: they have a single-bit flag register (T register) which is implicitly set by comparison
> operations and read by conditional branch instructions.
Motorola MCORE did that also, for the same reason (only 16-bit instructions, and with a single bit flag the branch displacement is enlarged by 3 bits, e.g. from 8 to 11).
Max
