TREZA (no.delete@this.ema.il) on February 17, 2013 11:59 am wrote:
> ⚛ (0xe2.0x9a.0x9b.delete@this.gmail.com) on February 17, 2013 10:49 am wrote:
> > > > Linus Torvalds (torvalds.delete@this.linux-foundation.org) on February
> > > > 14, 2013 4:44 pm In contrast, multiple CC registers are just stupid.
> >
> > Isn't it true that the following code could run faster with 2 CC registers:
> >
> > if a==b && c==d { ... }
> >
>
> It could be faster with in-order cores without branch prediction.
>
> For modern CPUs, it is mainly about the probablilistic results of the a==b and c==d tests.
>
> Having multiple CCs complexifies the management of flags and their
> various speculative values. This is bad for a advanced OoO CPU.

Continuing on the subject, the a==b && c==d is not probably the type of operation really needing multiple CC... except when the variables are floats (which should [almost] never be compared for equality, btw)

There are separate flags for FP and integer registers on x86 and ARMs.

Unlike PowerPCs, 64bits SPARCs use several condition codes (4 sets, IIRC) only for the FP registers.

I stand that multiple CCs are valuable when the following conditions are met :
- In-order, preferably superscalar.
- Non speculative, or with awful branch penalty.
- For FP registers or mixed FP/integer operations.
FP comparisons are sometimes more difficult to predict than integer ones.

Such CPUs disappeared at the beginning of the 21th century.

I wonder whether the FP and integer condition codes should be merged in a new architecture targetting high performance CPUs.