By: hobold (hobold.delete@this.vectorizer.org), February 20, 2013 2:02 pm
Room: Moderated Discussions
Paul A. Clayton (paaronclayton.delete@this.gmail.com) on February 19, 2013 5:52 pm wrote:
> EBFE (x.delete@this.y.com) on February 19, 2013 1:03 am wrote:
> [snip]
> > By "early branch resolution" you mean that the branch simply doesn't predict and stall for the condition?
>
> No, I was thinking of using early availability of a branch condition to potentially override any prediction.
This has been done in a family line of short pipelined (4 or 5 stages in total, IIRC) PowerPC processors. The model numbers were PPC603, PPC603e, PPC740, PPC750, PPC7400, PPC7410. I think some of those still live on as embedded core line, under names like "e300". All these processors could resolve conditional branches without prediction when the respective condition register field had no updates pending as the branch was encountered. If there were updates in flight, the branch was predicted as usual.
There were contemporary processor models by the same manufacturers with longer pipelines (and higher clock frequencies and generally higher performance) that did not even try to do this trick. Apparently it is not too effective as the machines get wider and deeper. It worked nicely for the simpler microarchitectures, though, and helped them to conserve energy as well.
> EBFE (x.delete@this.y.com) on February 19, 2013 1:03 am wrote:
> [snip]
> > By "early branch resolution" you mean that the branch simply doesn't predict and stall for the condition?
>
> No, I was thinking of using early availability of a branch condition to potentially override any prediction.
This has been done in a family line of short pipelined (4 or 5 stages in total, IIRC) PowerPC processors. The model numbers were PPC603, PPC603e, PPC740, PPC750, PPC7400, PPC7410. I think some of those still live on as embedded core line, under names like "e300". All these processors could resolve conditional branches without prediction when the respective condition register field had no updates pending as the branch was encountered. If there were updates in flight, the branch was predicted as usual.
There were contemporary processor models by the same manufacturers with longer pipelines (and higher clock frequencies and generally higher performance) that did not even try to do this trick. Apparently it is not too effective as the machines get wider and deeper. It worked nicely for the simpler microarchitectures, though, and helped them to conserve energy as well.
