Speculative multi-threading

By: David Kanter (dkanter.delete@this.realworldtech.com), January 3, 2014 2:12 am
Room: Moderated Discussions
Maynard Handley (name99.delete@this.name99.org) on January 3, 2014 12:06 am wrote:
> Maynard Handley (name99.delete@this.redheron9.com) on December 31, 2013 5:26 pm wrote:
> > Summary: I think it's true (and mostly agreed) that SW prefetching is dead. What's not widely known is
> > the extent of interesting HW replacements, or the extent to which any of these are yet implemented.
> In the context of what I wrote earlier, there seems to be an emerging consensus around future
> architectures that takes the form of slipping long-latency instructions (and their chains of
> dependent instructions, possibly hundreds to thousands of instructions long) aside to get at
> the independent instructions that can run. The details are now only in exactly how this is done
> so as to replace the ROB with as low power, low area, and low complexity as possible.
> Along these lines we have FlowForward, CPR (Checkpoint Processing and Recovery) and its successor/amplification
> CFP (Continual Flow Processing) and now I see DOE, Disjoint Out-of-Order Execution
> http://j92a21b.ee.ncku.edu.tw/broad/report100/2012-12-24/Disjoint%20OOO%20Execution%20Proc%2012.pdf
> Looked at from a thousand miles up, this last one, in particular, sounds somewhat like Apple's infamous MacroScalar
> stuff I mentioned in my last post... The details and the concentration differs, sure, but the abstract view
> seems, in all these cases, to be to create, on the fly, long long LONG chains of instructions such that all
> instructions in a chain are dependent, but the various chains are independent of each other (except to the extent
> that they fork from the occasional starting point, and join again at join point). Once you have these chains,
> it's a somewhat orthogonal question whether you run them on the same "CPU" (CFP, FlowForward), on kinda sorta
> but not quite the same CPU (MacroScalar), or different CPUs (kinda sorta the DOE stuff).
> Does anyone have an opinion on how real this stuff is? The CPR/CFP/DOE chain of ideas is
> based on people at Intel, but that obviously doesn't mean Intel are ready to bet on it.
> Part of me thinks it would take working silicon from a university (kinda like
> SPARC/MIPS in the 80s) to really validate the idea and make it worth swapping
> in for the tried and trusted OoO ROB engines that everyone uses today.
> And part of me hopes that Apple, as the one player in this space that has not been burned by over-ambition
> on the CPU front, might just be audacious enough to look at these numbers ("hmm, we can get a CPU that's about
> 50% faster than our existing A7, in smaller area and lower power, and that will scale well to higher frequencies.
> Hell, let's take on Intel and ARM head-on and go into the business of selling CPUs to everyone")
> Though I'd be just as happy if nVidia or Qualcomm or AMD were desperate enough to make
> a splash that they took these ideas and ran with them. I've been looking at a bunch of
> ideas for how to handle memory latency, and this collection seem the most promising.
> What worries me is that the gap between our optimized OoO engines today and the retooling you'd need for
> these alternative ideas is so large that it's not easy to get from here to there. I THINK you could do it
> in stages by starting with a simple (hah!) OoO core like an ARM9 or ARM15 and initially just replacing the
> ROB with checkpoints. With that working and giving you, say, 20%, you could then, next generation, replace
> the instruction window/scheduler with the CFP data buffers, giving you another 20% or so, and another sellable
> product, then finally add in the DOE weirdness to add a few more percent and speed up multi-threaded apps.
> But even with this slicing up, each stage is a fairly ambitious engineering project...

The investment in OOO is largely why I like speculative multi-threading - it can be used in conjunction with OOO and creates an orthogonal level of parallelism.

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                        Haskell Compilation Improvementanon2013/04/11 11:18 AM
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                          Inherent advantage of software prefetchJouni Osmala2013/04/11 09:41 PM
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                            Another example: software scatter gather (NT)Megol2013/04/14 02:39 AM
                          Haskell Compilation ImprovementMaynard Handley2013/12/31 05:26 PM
                            Haskell Compilation ImprovementTREZA2013/12/31 05:44 PM
                              Haskell Compilation ImprovementMaynard Handley2013/12/31 07:49 PM
                                Haskell Compilation Improvementanon2013/12/31 10:39 PM
                                  Haskell Compilation ImprovementMaynard Handley2014/01/01 02:04 AM
                                  Haskell Compilation Improvementbakaneko2014/01/01 05:31 AM
                                Haskell Compilation ImprovementGabriele Svelto2014/01/02 07:57 AM
                                  Haskell Compilation ImprovementMichael S2014/01/02 08:37 AM
                                    Haskell Compilation ImprovementGabriele Svelto2014/01/02 10:09 AM
                                    Haskell Compilation ImprovementTREZA2014/01/02 12:43 PM
                            Haskell Compilation ImprovementMaynard Handley2013/12/31 06:07 PM
                            Future core architectures. (Was Haskell Compilation Improvement)Maynard Handley2014/01/03 12:06 AM
                              Speculative multi-threadingDavid Kanter2014/01/03 02:12 AM
                                Speculative multi-threadingMaynard Handley2014/01/03 05:01 AM
                              Future core architectures. (Was Haskell Compilation Improvement)Seni2014/01/03 01:09 PM
                              Future core architectures. (Was Haskell Compilation Improvement)Linus Torvalds2014/01/03 01:27 PM
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            Software prefetch architectureMegol2013/04/15 11:03 AM
              Software prefetch architectureEric Bron2013/04/15 11:30 AM
  low barMichael S2013/04/09 04:38 PM
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