David Kanter (dkanter.delete@this.realworldtech.com) on April 23, 2013 12:15 pm wrote:
> someone (someone.delete@this.somewhere.com) on April 23, 2013 12:11 pm wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on April 23, 2013 8:14 am wrote:
> > > I just posted a new article online:
> > >
> > > Graphics is a focal point of the upcoming Haswell platform, necessitating a high bandwidth memory
> > > solution. To deliver high performance Intel is returning to the DRAM market, which it exited in
> > > 1985. The memory that ships with Haswell will be a custom embedded DRAM mounted in the package and
> > > manufactured on a variant of Intel’s 22nm process. By avoiding the commodity memory market, Intel
> > > will preserve high margins by cannibalizing discrete GPUs and dedicated graphics memory.
> > >
> > > http://www.realworldtech.com/intel-dram/
> > >
> > > As always, I encourage discussion, so let the fun begin!
> > >
> > > David
> >
> >
> > "Intel uses a trench capacitor to store the actual data bits. Unlike IBM’s work where the trench is dug
> > into the silicon substrate, Intel’s eDRAM forms a high aspect ratio trench above the transistors in the
> > metal interconnects and interlayer dielectrics and filled with a metal-insulator-metal capacitor."
> >
> > Hmmm? By definition a trench capacitor is a cap built deep down into the substrate
> >
> > Intel's DRAM cell cap would be a crown or stacked capacitor.
>
> Here's the way the advance program describes it:
>
> "A high aspect-ratio, 3-D metal-insulator-metal capacitor trench has been integrated into the
> ultra-low-k interlayer dielectric and Cu metallization used for interconnect stacks."
>
> I just got confused by the usage of teh 'capacitor trench' as opposed to 'trench capacitor'.
>
> DK

Weird nomenclature. Maybe they mean the cap is stacked high enough to
be an obstruction that blocks most/all interconnect layers.

From the perspective of the passivation layer the cell cap is a "trench cap". :-)