slacker (s.delete@this.lack.er) on April 23, 2013 10:30 pm wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on April 23, 2013 12:15 pm wrote:
> >
> > Here's the way the advance program describes it:
> >
> > "A high aspect-ratio, 3-D metal-insulator-metal capacitor trench has been integrated into the
> > ultra-low-k interlayer dielectric and Cu metallization used for interconnect stacks."
> >
> > I just got confused by the usage of teh 'capacitor trench' as opposed to 'trench capacitor'.
>
> Intel calls it a MIM cap ("Metal-insulator-Metal"), so it's not a trench capacitor (something fabricated
> within the substrate itself). Most CMOS processes that offer a MIM cap option will thin the second
> last oxide layer in the metal stack, then deposit an additional metal layer above this thin oxide. The
> metal layers above and below the thin oxide allow for the creation of parallel plate capacitors.

> From the description, it's impossible to tell whether Intel is manufacturing this MIM cap
> at the bottom, middle, or top of the metal stack. Using the term "capacitor trench" sounds
> like a typical Intel-ism (an unnecessary twisting of standard technical language).

According to the VLSI12 paper on the 22nm process, the MIM cap resides between M8 and M9 (M9 is the 14um one). So I'd assume that the MIM cap is sitting in the upper layers of metal. Also, the text seems to indicate that they are using a high-k dielectric for the capacitors.

David