Cache Chips Embedded in Package Substrate

Article: Intel’s Long Awaited Return to the Memory Business
By: AlbertH (please.delete@this.email.address), July 10, 2013 3:50 pm
Room: Moderated Discussions
After Haswell-E (maybe Broadwell-E), I think Intel will embed Crystalwell cache chips in the printed circuit board of the package substrate. They could put 4 Crystalwell chips on the 4 sides of a processor in the epoxy of the package substrate and 4 more Crystalwell chips on top of the package substrate. To do this, they would solder 4 Crystalwell chips to the bottom half of the package substrate. Then they would put a layer of epoxy and glass fiber on top of the 4 chips between the bottom half of the package substrate and the top half of the package substrate. Then they would heat and press this sandwich. Then they would drill and plate the vias. Then they would test the assembly. Finally, they would solder the processor and the top 4 Crystalwell chips to the top of the package substrate. This would provide 1 or 2 GBytes of cache using 128 MByte or 256 MByte Crystalwell chips. I expect this to first appear in the 4-socket Xeons. This 1 or 2 GBytes will be the last level of cache. There could be one or two smaller and faster cache chips on top of the processor in addition to this last level of cache. Part of the L3 cache in the processor could be repurposed to hold the tags for this enormous last level cache. Examples of applications for this type of assembly are in-memory databases such as SAP HANA and bioinformatics. This assembly could also be used in supercomputers with no additional DRAM. I don't have any confidential information so this is all speculation on my part.
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    Haswell DRAM DIMM latencyEduardoS2013/07/10 05:08 PM
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