By: AlbertH (please.delete@this.email.address), July 10, 2013 4:21 pm
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on April 29, 2013 5:56 am wrote:
> Will the processor have tags on-die to use it effectively as an L4 cache or
> will it be accessible as a scratchpad memory only for communicating with the GPU?
A presentation from Intel at IDF2013 Beijing describes the eDRAM as a cache that is "fully shared between graphics, media and cores". See slide 26 of session ARCS001, which you can download here:
http://intel.activeevents.com/bj13/scheduler/catalog.do
I haven't seen other details from Intel. The L4 cache tags are on the processor die. If the L4 cache tags were on the eDRAM, there would be a significant increase in latency to the DRAM DIMMs or the DRAM DIMM access would have to occur in parallel with the L4 cache tag look-up (which would waste power).
> Will the processor have tags on-die to use it effectively as an L4 cache or
> will it be accessible as a scratchpad memory only for communicating with the GPU?
A presentation from Intel at IDF2013 Beijing describes the eDRAM as a cache that is "fully shared between graphics, media and cores". See slide 26 of session ARCS001, which you can download here:
http://intel.activeevents.com/bj13/scheduler/catalog.do
I haven't seen other details from Intel. The L4 cache tags are on the processor die. If the L4 cache tags were on the eDRAM, there would be a significant increase in latency to the DRAM DIMMs or the DRAM DIMM access would have to occur in parallel with the L4 cache tag look-up (which would waste power).
