By: SHK (nomail.delete@this.mail.com), May 6, 2013 3:19 pm
Room: Moderated Discussions
> My detailed look at the microarchitecture is online: http://www.realworldtech.com/silvermont/
>
> Comments and questions are welcome, let the discussion begin!
>
> David
As always, best in-depth article on the web.
Just a small typo: on page 4, "the 16 architectural registers (RAX:RSP and R8-R15)" should be "... (RAX-RSP and R8-R15)".
Are the internal macro-ops similar to what intel's manuals call "microfused ops" (cracked to risc-uops at rename stage)?
Also, do you have any info on the implementation of SSE4.2 instructions (PCMPISTRI and similar).
>
> Comments and questions are welcome, let the discussion begin!
>
> David
As always, best in-depth article on the web.
Just a small typo: on page 4, "the 16 architectural registers (RAX:RSP and R8-R15)" should be "... (RAX-RSP and R8-R15)".
Are the internal macro-ops similar to what intel's manuals call "microfused ops" (cracked to risc-uops at rename stage)?
Also, do you have any info on the implementation of SSE4.2 instructions (PCMPISTRI and similar).