Very interesting as always, thanks!

I have a few questions and comments.

Don't you think Intel will fuse off 64-bit instructions at lower end or for smartphones?

Regarding TLB, you don't mention an L2 ITLB. Isn't what you call the L2 DTLB in fact a unified TLB for I and D?

I find 128 entries for L2 TLB rather small, that only covers half of the L2 cache.

I'm also surprised to find 16 entries for 2 MB pages. Are such pages that often in use? Vram and kernel mapping?

Also though I know power condumption of caches can be significant, I'm surprised the Dcache is still 24 KB.