By: Michael S (already5chosen.delete@this.yahoo.com), May 6, 2013 3:59 pm
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on May 6, 2013 2:30 pm wrote:
> Silvermont is Intel’s first CPU core tailored for power efficient applications such as smartphones,
> tablets, and microservers. The 22nm microarchitecture features updated instruction set extensions,
> full out-of-order execution with a tightly coupled L2 cache, aggressive power management, and a new
> high performance SoC fabric. These enhancements deliver tremendous performance and frequency gains
> over the aging Atom core, putting Intel’s mobile strategy in a more competitive position.
>
> My detailed look at the microarchitecture is online: http://www.realworldtech.com/silvermont/
>
> Comments and questions are welcome, let the discussion begin!
>
> David
Thank you, David, good article.
Two questions:
1. How Silvermont handles load-op and load-op-store x86 instructions. Are they cracked before ROB, consuming multiple ROB entries, or after ROBs, consuming just one entry?
2. Do store instructions generate 2 uOPs as on all previous Intel OoO cores or just 1 uOp. If the later, does it mean that memory EU has ability to do 3 integer register reads per clock?
> Silvermont is Intel’s first CPU core tailored for power efficient applications such as smartphones,
> tablets, and microservers. The 22nm microarchitecture features updated instruction set extensions,
> full out-of-order execution with a tightly coupled L2 cache, aggressive power management, and a new
> high performance SoC fabric. These enhancements deliver tremendous performance and frequency gains
> over the aging Atom core, putting Intel’s mobile strategy in a more competitive position.
>
> My detailed look at the microarchitecture is online: http://www.realworldtech.com/silvermont/
>
> Comments and questions are welcome, let the discussion begin!
>
> David
Thank you, David, good article.
Two questions:
1. How Silvermont handles load-op and load-op-store x86 instructions. Are they cracked before ROB, consuming multiple ROB entries, or after ROBs, consuming just one entry?
2. Do store instructions generate 2 uOPs as on all previous Intel OoO cores or just 1 uOp. If the later, does it mean that memory EU has ability to do 3 integer register reads per clock?
