By: David Kanter (dkanter.delete@this.realworldtech.com), May 6, 2013 4:48 pm
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on May 6, 2013 3:59 pm wrote:
> Thank you, David, good article.
>
> Two questions:
> 1. How Silvermont handles load-op and load-op-store x86 instructions. Are they cracked
> before ROB, consuming multiple ROB entries, or after ROBs, consuming just one entry?
Instructions only take a single ROB entry, there is no cracking.
> 2. Do store instructions generate 2 uOPs as on all previous Intel OoO cores or just 1 uOp. If
> the later, does it mean that memory EU has ability to do 3 integer register reads per >clock?
It's a single instruction. What do you need 3 reads for? Index+offset+data?
DK
> Thank you, David, good article.
>
> Two questions:
> 1. How Silvermont handles load-op and load-op-store x86 instructions. Are they cracked
> before ROB, consuming multiple ROB entries, or after ROBs, consuming just one entry?
Instructions only take a single ROB entry, there is no cracking.
> 2. Do store instructions generate 2 uOPs as on all previous Intel OoO cores or just 1 uOp. If
> the later, does it mean that memory EU has ability to do 3 integer register reads per >clock?
It's a single instruction. What do you need 3 reads for? Index+offset+data?
DK
