By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), May 6, 2013 9:27 pm
Room: Moderated Discussions
none (none.delete@this.none.com) on May 6, 2013 3:32 pm wrote:
[snip]
> I'm also surprised to find 16 entries for 2 MB pages. Are
> such pages that often in use? Vram and kernel mapping?
There is, of course, the highly unlikely possibility that the huge page TLB entries are also used to cache PDEs (as I have often suggested). If that was the case, the number of entries might be even larger and still be reasonably useful. Since neither Intel nor AMD have ever done this (but instead used separate caching structures for PDEs et al.), I am extremely skeptical that such flexibility is supported.
For servers, 2MiB pages might find significant use. I would also not be surprised if a unified VM (Davlik??) or a web browser could exploit 2MiB pages even with only 1GiB of memory.
[snip]
> I'm also surprised to find 16 entries for 2 MB pages. Are
> such pages that often in use? Vram and kernel mapping?
There is, of course, the highly unlikely possibility that the huge page TLB entries are also used to cache PDEs (as I have often suggested). If that was the case, the number of entries might be even larger and still be reasonably useful. Since neither Intel nor AMD have ever done this (but instead used separate caching structures for PDEs et al.), I am extremely skeptical that such flexibility is supported.
For servers, 2MiB pages might find significant use. I would also not be surprised if a unified VM (Davlik??) or a web browser could exploit 2MiB pages even with only 1GiB of memory.
