none (none.delete@this.none.com) on May 6, 2013 3:32 pm wrote:
> Very interesting as always, thanks!
>
> I have a few questions and comments.
>
> Don't you think Intel will fuse off 64-bit instructions at lower end or for smartphones?
>
> Regarding TLB, you don't mention an L2 ITLB. Isn't what
> you call the L2 DTLB in fact a unified TLB for I and D?
>
> I find 128 entries for L2 TLB rather small, that only covers half of the L2 cache.
>
> I'm also surprised to find 16 entries for 2 MB pages. Are
> such pages that often in use? Vram and kernel mapping?

Modern Linux kernels are able to use 2MB pages transparently to the user process, merging and breaking pages as needed. Right now, if you boot a modern kernel, almost all anonymous memory that was requested in chunks of over 2MB is backed by 2MB pages, and this will likely be expanded to different classes of memory over time.

doc: https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/Documentation/vm/transhuge.txt?id=refs/tags/next-20130507