EduardoS (no.delete@this.spam.com) on May 7, 2013 7:18 pm wrote:
> Linus Torvalds (torvalds.delete@this.linux-foundation.org) on May 7, 2013 3:07 pm wrote:
> > Umm. You missed the most important number. L2 size/latency.
>
> That's true, but I only have the size from each, wich is 512kB
> per core for both, no reliable source for latency numbers.
>
The SOG for AMD Family 16h says: 'The L2 cache has a variable load-to-use latency of no less than 25 cycles.'

Silvermont shares 1MB L2 between 2 cores in 'module'. JG shares its 2MB L2 among all 4 cores. It's 521kB/core in both cases. However, there is a possibility to use the entire 2MB for a single core in JG compared to 1MB in Intel's case.

Obviously there are many trade-offs, increased latency being surely one of them.

Anyway, there is a main difference in the man. process - Intel's 22nm vs TSMC's 28nm. Intel's should be superior thus allow higher freq.