By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), May 8, 2013 4:27 am
Room: Moderated Discussions
Paul A. Clayton (paaronclayton.delete@this.gmail.com) on May 6, 2013 9:00 pm wrote:
> (though SMT is less useful in a narrow [and somewhat shallow] OoO microarchitecture).
Oracle demonstrated with the SPARC T4 that SMT can be beneficial for narrow architectures too though in their case SMT leverages a memory subsystem which has significantly higher latency and allows for many more concurrent accesses.
My guess is that having both OoOE and SMT would exceed the power-budget Intel had in mind and possibly add excessive complexity to the validation of an already brand new micro-architecture. Since the fundamental module would be dual-core anyway it wasn't worth the risk; maybe we'll see it again in a future iteration.
> (though SMT is less useful in a narrow [and somewhat shallow] OoO microarchitecture).
Oracle demonstrated with the SPARC T4 that SMT can be beneficial for narrow architectures too though in their case SMT leverages a memory subsystem which has significantly higher latency and allows for many more concurrent accesses.
My guess is that having both OoOE and SMT would exceed the power-budget Intel had in mind and possibly add excessive complexity to the validation of an already brand new micro-architecture. Since the fundamental module would be dual-core anyway it wasn't worth the risk; maybe we'll see it again in a future iteration.
