Patrick Chase (patrickjchase.delete@this.gmail.com) on May 17, 2013 5:49 pm wrote:
> Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on May 15, 2013 5:37 pm wrote:
> > Ashraf Eassa (aeassa.delete@this.gmail.com) on May 15, 2013 11:59 am wrote:
> > > A couple of questions then:
> > >
> > > 1. How can a narrower design pull this off?
> >
> > It doesn't. Not without trickery anyway - like comparing a highly clocked CPU
> > against a low clocked one
>
> You've heard the terms "brainiac" and "speed demon" before in the context of microarchitecture,
> right? If you, then you are unboubtedly aware that there is a very real tradeoff between "narrow
> but fast" and "slow but wide", and that both approaches have both proven to be viable approaches
> at various times depending on the constraints (process, objectives, etc).
>
> A15 is wider than Silvermont, but Silvermont appears to hit higher clock rates on current
> processes. In that case it's entirely legitimage to "compare [a] highly clocked CPU against
> a low clocked one", since the differences in width and clock rate reflect legitimate architectural
> tradeoffs. All that matters is that the processes so compared are contemporary.
>
> More broadly, you and many others in this thread seem to be overestimating the importance of architecture.
> The analogy I like is that of microarchitecture to a card game. ISA, process, and constraints (power, cost,
> area, R&D investment, etc) are the cards that the microarchitect is dealt at the outset. How [s]he plays
> those cards is at least as important to the final outcome (think "bridge" rather than "blackjack").
>
> History has shown us that ISA is MUCH less important than people on forums like this
> one like to pretend. Process arguably matters more, and the quality of the design team
> (gameplay in the analogy above) and level of investment are at least as important.
>
> In the case of Silvermont vs A15, I suspect that the following two factors account
> for Intel's claimed advantage (assuming for the moment that it's real):
>
> 1. Process. Intel are comparing 22 nm FinFET to 28 nm planar. That's an entirely legitimate
> comparions inasmuch as Intel made the investment to create that 22 nm process.
>
> 2. Design. Intel is historically very good at physical design and custom libraries. The difference
> between that and a fully synthesized core on a standard library should arguably swamp ISA even
> on the same process. Does anybody know what Samsung did with the A15s on Exynos?
>

ISA isn't everything but if you get it sufficiently wrong it can kill your architecture in the long run. I'm thinking particularly of earlier RISC designs, which made high memory efficiency nearly impossible due to lack of byte addressing and inefficient instruction coding, things that were killers once the speed of CPU cores and memory began to diverge in earnest. The lack of integer divide, etc. The last could easily have been fixed efficiently with a fast emulator trap (we saw such things later). It felt as if these ISA designers had never done any real world programming.