Paul A. Clayton (paaronclayton.delete@this.gmail.com) on May 18, 2013 3:48 pm wrote:
> (Such is a little surprising in that MIPS is relatively register rich, so the
> benefit of having such a temporary storage would seem to be very small, though perhaps
> some such cases might allow the avoidance of a register-register move?)

Could have happened completely by accident. Like someone moved around some instructions and didn't realize they put the load behind the access to it, but it still worked.

> Does anyone here know if cache misses filled the load destination before the value would
> be read by a delay slot instruction? (I could not find the reference I vaguely recall reading
> on comp.arch, but I did not search intently and my search skills are not great.)

In this case (PS1's CPU) there was no data cache, just a scratchpad and main memory DRAM. I assume the timings for the latter weren't constant but I really don't know. It's possible that wait states to externally memories stalled the entire core, preventing any problems with the pipeline state getting messed up. Cache misses on other processors could have worked the same way.