By: David Kanter (dkanter.delete@this.realworldtech.com), May 21, 2013 1:54 pm
Room: Moderated Discussions
> The thing is that Intel already knows how to do good, performant, power efficient cores.
> There is two decades of experience there, you don't *need* to go back to Pentium core.
>
> They could have started with a pentium-m ish core, and probably had a much easier ability to take improved
> structures from later cores and even share their own improvements back to the high performance line.
I don't think that's true. The fundamental structures for memory and instruction reordering in the P6-derivatives and Silvermont are VERY different. P6+ are all designed for multiple load/store per clock, which has a real impact on your design space. Silvermont is a very good design which has much smaller CAMing structures (e.g., LD/ST buffers). I don't think there's any real way to get from P6 to that point.
> I think the reason they did not do that is because management
> is petrified about cannibalizing their own high margin lines.
That was certainly a concern.
David
> There is two decades of experience there, you don't *need* to go back to Pentium core.
>
> They could have started with a pentium-m ish core, and probably had a much easier ability to take improved
> structures from later cores and even share their own improvements back to the high performance line.
I don't think that's true. The fundamental structures for memory and instruction reordering in the P6-derivatives and Silvermont are VERY different. P6+ are all designed for multiple load/store per clock, which has a real impact on your design space. Silvermont is a very good design which has much smaller CAMing structures (e.g., LD/ST buffers). I don't think there's any real way to get from P6 to that point.
> I think the reason they did not do that is because management
> is petrified about cannibalizing their own high margin lines.
That was certainly a concern.
David