> - Qualcomm Hexagon (at least the versions I'm familiar with) has 32 GPRs for 4 units, but with a fairly
> short pipeline (load->use delay of 2-3 clocks if memory serves). It saves instruction encoding bits
> by using partial predication, i.e. some instructions have predicated forms while others don't.

Is there any public documentation on this architecture?

Or Qualcomm GPUs for that matter?

DK