By: Exophase (exophase.delete@this.gmail.com), May 23, 2013 11:45 am
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on May 23, 2013 11:19 am wrote:
> > - Qualcomm Hexagon (at least the versions I'm familiar with) has 32 GPRs for 4 units, but with a fairly
> > short pipeline (load->use delay of 2-3 clocks if memory serves). It saves instruction encoding bits
> > by using partial predication, i.e. some instructions have predicated forms while others don't.
>
> Is there any public documentation on this architecture?
>
> Or Qualcomm GPUs for that matter?
>
> DK
>
https://developer.qualcomm.com/hexagon-processor
> > - Qualcomm Hexagon (at least the versions I'm familiar with) has 32 GPRs for 4 units, but with a fairly
> > short pipeline (load->use delay of 2-3 clocks if memory serves). It saves instruction encoding bits
> > by using partial predication, i.e. some instructions have predicated forms while others don't.
>
> Is there any public documentation on this architecture?
>
> Or Qualcomm GPUs for that matter?
>
> DK
>
https://developer.qualcomm.com/hexagon-processor
