David Kanter (dkanter.delete@this.realworldtech.com) on May 23, 2013 11:19 am wrote:
> > - Qualcomm Hexagon (at least the versions I'm familiar with) has 32 GPRs for 4 units, but with a fairly
> > short pipeline (load->use delay of 2-3 clocks if memory serves). It saves instruction encoding bits
> > by using partial predication, i.e. some instructions have predicated forms while others don't.
>
> Is there any public documentation on this architecture?

There used to be. I have a copy of the programmer's reference for v2, that was freely available from qualcomm.com. Since then they've gotten a bit tighter though they've published some conference papers about their compiler work (they added Hexagon scheduling to LLVM to deal with certain workloads at runtime).

Josh Fisher did a bit of digging a while back (he has an interest in such things for some odd reason) so I can ping and see what he's got.

> Or Qualcomm GPUs for that matter?

I personally don't have any. Adreno is the old BitBoys/ATI mobile design (one of the most infamous pieces of vaporware, solidified) and there's a bunch of stuff out there about those.