Sebastian Soeiro (sebastian_2896.delete@this.hotmail.com) on May 28, 2013 4:27 pm wrote:

> not being totally optimal; though, to my understanding, doesnt Haswell go the traditional route
> of using the Unified Scheduler to send the instructions through ports directly to the ALU functions?

Yes, it does.
> I mean, I'm sure it's more than robust enough to have atleast one instruction to run through atleast
> most of the time; but can't it only dispatch one instruction per clk? Or can it send dispatches
> through any combination of open ports the second instructions become ready?

The later.It can send an instruction to each port every clock.
As long as there are instructions ready to be executed and suitable ports, of course.

> The load unit? I've looked over the Silvermont article and found little mention of it-- maybe I'm
> skipping over it or my brain just isnt comprehending it under a different name or something... Could
> you please point me to the right direction as to where I could learn more about the load unit?

Sorry, it's not named "load unit".
It's the logic blocks below the 6 entry memory reservation station.

Here's a diagram which may be a bit clearer for this purpose:
http://www.extremetech.com/wp-content/uploads/2013/05/silvermont-core-block-diagram.jpg

It only shows the path from the L1 data cache to the integer register renamer, but I guess it also goes to the FP/SIMD registers.