Silvermont architecture in-depth article

Article: Silvermont, Intel's Low Power Architecture
By: Ricardo B (ricardo.b.delete@this.xxxxx.xx), May 30, 2013 11:18 am
Room: Moderated Discussions
Sebastian Soeiro (sebastian_2896.delete@this.hotmail.com) on May 30, 2013 9:48 am wrote:

> - So it seems to me that the AGU almost computes a "tag" for the CPU to use to refer themselves to
> the actual data entires, whilst the DTLB holds the actual physical location of these data entries?
> Or do I still have something wrong? The AGU seems very ambigious to me... Or perhaps the AGU is the
> unit that requests data to be fed to the other execution units? Recieving instructions from the scheduler
> to request certain data entries, which moves onto the DTLB which moves to the L1/L2?


There are two (main) types of memory addresses in a modern CPU: virtual and physical.
In general, software handles virtual address.

The operative system sets up a page table, which is just a big look up table which maps pages (4KB in x86) of virtual addresses into physical addresses and also contains access permissions.

Ie, something like
Virtual address => physical address, permissions, etc
0x00000000 => 0x19831, read, write, no execute
0x00000001 => 0x32911, read, no write, execute
...
This mechanism is required for any operative system more robust than DOS.

But before we go to the page table, an x86 instruction which accesses memory can use pretty complicated addressing, such as DS:EBX + 4*ESI + 39;
The AGU does all the math and comes up with a single number, which is called the virtual address.

The DTLB then performs a look up in the page table, to convert the virtual address into a physical memory address, permission bits, etc


> - So the store buffer is very unclear to me. Your explanation probably makes perfect sense,
> it's just me who probably doesnt understand. Though what I don't understand is; where do these
> store requests come from? I understand that the store buffer holds data before it is commited
> to the data caches, but where does this data come from? The execution units? If so, why would
> it be redirected back to the data caches if they were already "done" with?

The stores come from instructions which store data into memory.

> - So the prefetcher sortof acts like the data part of a loop detector? Or other patterns?

Yep, probably something like that. Only Intel and God know the details.
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                                                Exploiting for SMT was my "contribution"Paul A. Clayton2013/06/03 04:53 AM
                                            Silvermont architecture in-depth articleMichael S2013/06/01 10:49 AM
                        Silvermont architecture in-depth articleRicardo B2013/05/30 04:41 PM
                          Didn't notice how this was to be organized...Sebastian Soeiro2013/05/30 07:55 PM
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      No out-of-order in FP cluster of silvermont?Exophase2013/06/28 01:54 PM
        No out-of-order in FP cluster of silvermont?Michael S2013/06/29 11:21 AM
          No out-of-order in FP cluster of silvermont?Exophase2013/06/29 09:07 PM
      No out-of-order in FP cluster of silvermont?Linus Torvalds2013/06/29 12:22 PM
        No out-of-order in FP cluster of silvermont?anon2013/06/29 05:26 PM
          No out-of-order in FP cluster of silvermont?EduardoS2013/06/29 06:50 PM
            No out-of-order in FP cluster of silvermont?anon2013/06/29 09:15 PM
              No out-of-order in FP cluster of silvermont?EduardoS2013/06/29 09:31 PM
                No out-of-order in FP cluster of silvermont?anon2013/06/30 02:53 AM
                  No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 05:24 AM
                    No out-of-order in FP cluster of silvermont?anon2013/06/30 10:41 AM
                      No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 01:26 PM
                        No out-of-order in FP cluster of silvermont?anon2013/07/01 12:32 AM
                          No out-of-order in FP cluster of silvermont?EduardoS2013/07/01 05:40 PM
                            No out-of-order in FP cluster of silvermont?anon2013/07/01 06:44 PM
                            No out-of-order in FP cluster of silvermont?Michael S2013/07/02 05:40 AM
                              No out-of-order in FP cluster of silvermont?Exophase2013/07/02 09:03 AM
                              No out-of-order in FP cluster of silvermont?EduardoS2013/07/02 05:20 PM
                          No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 09:25 AM
                      No out-of-order in FP cluster of silvermont?Etienne2013/07/02 04:36 AM
                        No out-of-order in FP cluster of silvermont?anon2013/07/02 07:13 AM
                          No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 10:03 AM
                            No out-of-order in FP cluster of silvermont?anon2013/07/02 04:12 PM
                              No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 04:43 PM
                                No out-of-order in FP cluster of silvermont?anon2013/07/02 05:47 PM
                                  No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 07:36 PM
                                    No out-of-order in FP cluster of silvermont?anon2013/07/02 09:03 PM
                                      No out-of-order in FP cluster of silvermont?Symmetry2013/07/03 07:14 AM
                                        No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/03 09:04 PM
                                          No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/04 03:23 AM
                        No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 10:01 AM
                          No out-of-order in FP cluster of silvermont?Etienne2013/07/03 03:26 AM
                            layer 2 cache behaviourEtienne2013/07/05 03:14 AM
                              layer 2 cache behaviourMichael S2013/07/05 06:41 AM
                                layer 2 cache behaviourEtienne2013/07/05 09:15 AM
                              layer 2 cache behaviourPatrick Chase2013/07/05 11:37 AM
                                layer 2 cache behaviourMichael S2013/07/06 10:57 AM
                                  layer 2 cache behaviourPatrick Chase2013/07/06 12:08 PM
                                    layer 2 cache behaviourPatrick Chase2013/07/06 12:19 PM
                                    layer 2 cache behaviourEtienne2013/07/08 03:10 AM
                                      layer 2 cache behaviourPatrick Chase2013/07/08 10:02 AM
                                  layer 2 cache behaviourPatrick Chase2013/07/06 02:15 PM
                                  layer 2 cache behaviourUngo2013/07/09 03:24 PM
                      No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 08:43 AM
                  No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 08:34 AM
                    No out-of-order in FP cluster of silvermont?anon2013/07/02 04:15 PM
            No out-of-order in FP cluster of silvermont?none2013/06/30 05:03 AM
              No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 05:45 AM
                No out-of-order in FP cluster of silvermont?none2013/06/30 06:28 AM
                  No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 01:27 PM
        No out-of-order in FP cluster of silvermont?x2013/06/30 03:54 AM
          No out-of-order in FP cluster of silvermont?Foo_2013/06/30 06:15 AM
        No out-of-order in FP cluster of silvermont?rwessel2013/06/30 10:11 PM
          No out-of-order in FP cluster of silvermont?Linus Torvalds2013/07/01 01:40 PM
            No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 10:35 AM
              No out-of-order in FP cluster of silvermont?Linus Torvalds2013/07/02 11:18 AM
            FPU in integer codes2013/07/02 11:38 AM
              FPU in integer codesPatrick Chase2013/07/02 11:56 AM
              FPU in integer codesLinus Torvalds2013/07/02 12:12 PM
                FPU in integer codesPatrick Chase2013/07/02 12:34 PM
                  FPU in integer codesLinus Torvalds2013/07/02 01:55 PM
        No out-of-order in FP cluster of silvermont?2013/06/30 11:42 PM
          No out-of-order in FP cluster of silvermont?bakaneko2013/07/03 03:54 AM
        What about integer SIMD?Exophase2013/07/01 12:44 AM
          What about integer SIMD?anon2013/07/01 01:45 AM
            What about integer SIMD?Michael S2013/07/01 08:57 AM
              What about integer SIMD?rwessel2013/07/01 03:39 PM
                What about integer SIMD?Michael S2013/07/01 04:11 PM
                  What about integer SIMD?EduardoS2013/07/01 06:04 PM
                    What about integer SIMD?Michael S2013/07/02 12:32 AM
          What about integer SIMD?hi2013/07/01 08:15 AM
            What about integer SIMD?Exophase2013/07/01 10:50 AM
            What about integer SIMD?David Kanter2013/07/02 01:20 PM
              What about integer SIMD?hi2013/07/02 03:48 PM
                What about integer SIMD?David Kanter2013/07/04 03:19 PM
  Silvermont architecture in-depth articleSebastian Soeiro2013/07/30 09:34 AM
    TLBs are caches of page tablesPaul A. Clayton2013/07/30 11:03 AM
      TLBs are caches of page tablesSebastian Soeiro2013/07/30 01:18 PM
        TLBs are caches of page tablesPaul A. Clayton2013/07/30 03:59 PM
          TLBs are caches of page tablesSebastian Soeiro2013/07/30 05:27 PM
            TLBs are caches of page tablesrwessel2013/07/30 07:01 PM
              TLBs are caches of page tablesSebastian Soeiro2013/07/31 02:15 PM
                Floorplan images show physical locationsPaul A. Clayton2013/07/31 04:11 PM
                  Floorplan images show physical locationsSebastian Soeiro2013/07/31 09:12 PM
                    Floorplan images show physical locationsrwessel2013/08/01 12:21 AM
                      Floorplan images show physical locationsSebastian Soeiro2013/08/02 12:58 PM
                        Floorplan images show physical locationsAntti-Ville Tuunainen2013/08/02 02:09 PM
                        Floorplan images show physical locationsStubabe2013/08/02 07:49 PM
                          Floorplan images show physical locationsSebastian Soeiro2013/08/03 08:23 AM
                            Floorplan images show physical locationsrwessel2013/08/03 11:16 PM
                            Floorplan images show physical locationsMelody Speer2013/08/04 04:11 AM
                              Floorplan images show physical locationsSebastian Soeiro2013/08/04 05:42 PM
                                Floorplan images show physical locationsrwessel2013/08/04 10:58 PM
                                  Floorplan images show physical locationsSebastian Soeiro2013/08/07 03:33 PM
                                    Floorplan images show physical locationsrwessel2013/08/08 01:03 PM
                                      Floorplan images show physical locationsSebastian Soeiro2013/08/11 09:20 AM
                                        Page tables are set up by the OSPaul A. Clayton2013/08/11 01:25 PM
                                          Page tables are set up by the OSSebastian Soeiro2013/08/16 08:43 PM
                                            Multilevel page table formatPaul A. Clayton2013/08/17 11:18 AM
                                              Multilevel page table formatSebastian Soeiro2013/08/19 03:28 PM
                                                Multilevel page table formatrwessel2013/08/20 12:08 AM
                                                  Multilevel page table formatSebastian Soeiro2013/08/22 04:52 PM
                                                    Multilevel page table formatTREZA2013/08/22 05:30 PM
                                                    Multilevel page table formatrwessel2013/08/23 10:58 PM
                                                      Multilevel page table formatSebastian Soeiro2013/08/25 08:20 AM
                TLBs are caches of page tablesrwessel2013/08/01 12:41 AM
                  TLBs are caches of page tablesSebastian Soeiro2013/08/02 12:51 PM
                    TLBs are caches of page tablesrwessel2013/08/02 06:55 PM
  Silvermont instruction schedulingHugo Décharnes2013/10/02 03:25 AM
    Silvermont instruction schedulingMichael S2013/10/02 04:29 AM
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