Silvermont architecture in-depth article

Article: Silvermont, Intel's Low Power Architecture
By: rwessel (robertwessel.delete@this.yahoo.com), May 31, 2013 3:11 pm
Room: Moderated Discussions
Sebastian Soeiro (sebastian_2896.delete@this.hotmail.com) on May 31, 2013 2:26 pm wrote:
> rwessel (robertwessel.delete@this.yahoo.com) on May 31, 2013 10:59 am wrote:
> > Sebastian Soeiro (sebastian_2896.delete@this.hotmail.com) on May 31, 2013 8:01 am wrote:
> > > Klimax (danklima.delete@this.gmail.com) on May 31, 2013 7:15 am wrote:
> > > > Simple example: Due to bug (like unchecked end of array) it will write past allocated range. (Or just
> > > > randomly all over memory) And in process it will destroy whatever it can including kernel structure.
> > > > For crazy reading about crazy programs I recommend http://ptgmedia.pearsoncmg.com/images/9780321440303/samplechapter/Chen_bonus_ch02.pdf
> > > > Bonus chapter for book "The Old New Thing" by Raymond Chen.
> > > >
> > > > As for contiguous memory - arrays. (Enables simple and fast way to access
> > > > any element while knowing only starting address and size of structure)
> > >
> > > Thank you for your reply;
> > >
> > > Now I understand how virtual addresses can help arrays through contiguous addresses. I
> > > suppose where the physical addresses is the DTLB's problem; but the ALU math is probably
> > > vastly simplified by having contiguous virtual memory to calculate like (array+2) instead
> > > of (YMM15*14/2^3), and there are probably other benefits that I'm not even seeing.
> > >
> > > However, one question. Say an array has an error and just continues writing more and more and more
> > > elements to the array, filling memory. How would having contiguous virtual addresses prevent this
> > > from happening? I can see how it'd make it much easier to "clear" the memory of these errored entries,
> > > but is there a mechanism in place to detect if this error array is happening to stop it?
> >
> >
> > By itself, virtual address translation won't stop it, but eventually the bad application
> > will attempt to write to an address that is not valid in that process's (virtual) address
> > space, and the CPU will generate an exception, which the OS will catch, and then (usually)
> > terminate the offending process. When the offending process is terminated, all of its resources,
> > including memory allocations, are released by the OS, which tracks such things.
> >
> > Note that on most processors virtual addresses and physical address are very similar, occupying a flat
> > series of consecutive addresses. For example, on most 32 bit processors (supporting VM), addresses, both
> > virtual and physical, range from 0 to 4,294,967,295 (4GiB). Those address spaces are commonly divided
> > into 1,048,576 consecutive pages of 4096 bytes (4KiB). Many processors can turn off address translation,
> > and the any running code would then just access a physical address. Address translations basically sets
> > up a table to translate those million virtual page numbers for a process to physical page numbers. With
> > address translation on, a process wanting (say) 12KB of memory might get that assigned to virtual pages
> > 100, 101 and 102, and thus would access those as 12K consecutive addresses starting at (virtual) address
> > 409,600. Those three virtual pages might be mapped to physical pages 1000, 9876, and 123467, at the OS's
> > whim. Absent a specific request to share them, those three physical pages would *not* be mapped into any
> > other process's virtual address space, and so would only
> > be accessible to the one process. And while actual
> > virtual memory is less relevant these days, the OS might need more physical pages for one process and it
> > might page one of those virtual pages to disk, freeing up the associated physical page. When the process
> > tries to access that paged-out page, the OS will catch the associated exception, read the needed physical
> > page back into memory, fix up the translation, and let the application continue.
> >
> > In some situations, guard pages are generated adjacent to certain areas of (virtual) memory,
> > which allows running off the end of arrays to be caught fairly quickly. It's a limited solution
> > at best, since pages are too large to waste on small objects in most cases.
> >
> > But having a separate virtual address space prevents the errant process for trashing the
> > memory assigned to *other* processes. So while the buggy word processor dies a horrible
> > death, taking your document with it, the spreadsheet you were editing at the same time continues
> > running as if nothing had happened. Of course some processes cooperate and communicate with
> > each other, and will often react badly to one of the partners suddenly dying.
> >
>
> Ah, that all makes sense! So the OS can detect when things go
> rogue and kills off buggy processes! That's quite logical!
>
> Everything you said makes sense, and I definitely am learning
> quite a bit from it. But I have one outstanding question;
>
> You said that the OS usually uses 4KB pages, right? Well, how come Haswell has support for 4MB and
> 1GB pages? What benefit do these extra page sizes grant if the OS can only assign 4KB pages?
>
> Thank you for your very informative reply!


Obviously the OS needs to support larger pages in order to make use of them, but in most implementations, an OS not wanting to use than can just ignore them. These are often called superpages.

x86 CPUs have supported 2MB pages with the 8 byte (PAE style) page tables for quite some time. 4MB pages existed along with a different set of address space extensions, known as PSE, and these are largely irrelevant now - most OSs, even in 32 bit mode, use the PAE format page tables because it provides access to the "NX" page access bit).

On x86 (and many other systems, but certainly not all), page tables are basically arranged in a tree. Non-PAE page tables in x86 use a 4K "page directory" pointing to 1024 (4KB) page tables, each of which contains a four byte page table entry, which maps one virtual page to a physical page (or says the mapping is invalid). That 1024 x 1024 leads to the million page tables entries needed to map the entire 32 bit address space.

A separate copy of that tree exists for each address space (roughly synonymous with "process" in this context).

An important factor is that not all 1024 entries in the page directory need be populated (for example, if an entire aligned 4MB region is unmapped, that can be handled my marking the entry in the page directory invalid, which avoids the need to provide for an entire 4KB page table with nothing but invalid slots in it. This considerably compresses the size of the page table tree (otherwise each address space would need 4MB of translation table). Shared areas are created by having two page tables map the same physical page(s).

With PAE, page table entries are lengthened to eight bytes each (which leaves room for more physical address bits, as well as other control bits, like the NX bit). But since the page tables remain 4KB each, each level of page table only maps 512 entries (rather than 1024 in the non-PAE case), so that a single page directory entry only maps a 2MB region of memory (since it points to a page table that now has only 512 entries). So there are more levels of page table (three, if you use PAE in 32 bit mode, up to four* total in 64 bit mode). The third level of page table maps 1GB per entry, the fourth 512GB per entry.

The first (and smaller) advantage or large pages is that you can map large amounts of storage without having to construct page tables down to the 4KB page level. For example, with 2MB pages, you can map the entire 4GB address space with four page directory pages (totaling 16KB, plus 32 bytes for the PDPTEs). Newer processors have allowed pages to be defined at the third page table level as well, hence the 1GB pages.

Logically, after the CPU generates the virtual address is walks the page table until if finds the page table entry needed to determine the physical page assignment. In practice doing that would be horrible (even with two level page tables, you've now tripled the number of memory accesses needed for any memory reference). That's why we have TLBs. TLBs are special caches that remember frequently used translations. SO if you accessed virtual page 12345, the first time the CPU would have to walk the page time to find out that that was actually on physical page 9876. The second time, however, that information will be available in the TLB, where it can be accessed much, much faster.

Unfortunately there are two conflicting design goals for TLBs - large size and speed. A large TLB (or really, any cache) will necessarily be slow. The big advantage of large pages is that it can allow the TLB to map much more storage with the same number of entries. There have, of course been implementation details the mess things up some, for example, some implementations have used separate large and small page TLBs, with the large page TLBs being very small - indiscriminately making lots of large pages with a very small large page TLB will quickly cause that to thrash. So an OS needs to somewhat carefully manage large pages. The other downside to large pages is that they are, in fact, units - the OS is stuck dealing with the large page as a whole (IOW it cannot assign only a partial large page to an address space), which may lead to wasted memory if the OS is not careful.



*That's not enough to map the entire 64 bit address space, but extending that to five or sex levels would be straight-forward enough, although there will be additional issues to deal with when address spaces get that large.
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                      quad-core since Nov 2006mpx2013/05/13 01:34 AM
                        quad-core since Nov 2006RichardC2013/05/13 03:48 AM
                          quad-core since Nov 2006Jukka Larja2013/05/14 11:34 AM
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                            SMT is a dodo birdRicardo B2013/05/13 06:13 AM
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                               4C/4T 4.0GHz was significantly faster than 4C/4T 3.8GHz??Mark Roulo2013/05/14 05:37 PM
                                 4C/4T 4.0GHz was significantly faster than 4C/4T 3.8GHz??RichardC2013/05/14 05:54 PM
                                  Thanks. Mark Roulo2013/05/14 06:05 PM
                                   4C/4T 4.0GHz was significantly faster than 4C/4T 3.8GHz??Exophase2013/05/14 08:10 PM
                                     More tests of HT and gamesExophase2013/05/14 08:24 PM
                                       More tests of HT and gamesRichardC2013/05/15 03:26 AM
                                         More tests of HT and gamesExophase2013/05/15 06:43 AM
                                           More tests of HT and gamesMichael S2013/05/15 12:35 PM
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                          SMT is a dodo birdJukka Larja2013/05/15 09:02 AM
                        SMT is a dodo birdPatrick Chase2013/05/17 09:43 AM
                          SMT is a dodo birdJouni Osmala2013/05/17 10:27 AM
                          SMT is a dodo birdBrett2013/05/17 07:26 PM
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                  SMT is a dodo birdRichardC2013/05/12 06:57 AM
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                SMT is a dodo birdStubabe2013/05/14 12:09 PM
                  SMT is a dodo birdRichardC2013/05/14 01:43 PM
                    SMT is a dodo birdRicardo B2013/05/14 03:00 PM
                      SMT is a dodo birdRichardC2013/05/14 06:27 PM
                        SMT is a dodo birdRicardo B2013/05/15 03:50 AM
                          SMT is a dodo birdRichardC2013/05/15 08:53 AM
                            SMT is a dodo birdRicardo B2013/05/15 09:31 AM
                              SMT is a dodo birdRichardC2013/05/15 11:13 AM
                                SMT is a dodo birdRicardo B2013/05/15 12:43 PM
                                  SMT is a dodo birdRichardC2013/05/15 01:15 PM
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                                      SMT is a dodo birdRichardC2013/05/15 02:00 PM
                                        SMT is a dodo birdMaynard Handley2013/05/15 03:55 PM
                                        SMT is a dodo birdJouni Osmala2013/05/16 03:16 AM
                    SMT is a dodo birdStubabe2013/05/16 11:54 AM
                  Using the available die areaDoug S2013/05/14 05:51 PM
                    Using the available die areaRicardo B2013/05/15 04:15 AM
                      Using the available die areaStubabe2013/05/16 11:26 AM
                        Using the available die areaRicardo B2013/05/16 02:05 PM
      SMT is a dodo birdmpx2013/05/10 11:51 PM
        SMT is a dodo birdFoo_2013/05/11 05:21 AM
          SMT is a dodo birdEduardoS2013/05/11 09:28 AM
        SMT is a dodo birdDoug S2013/05/11 10:49 AM
          SMT is a dodo birdmpx2013/05/12 12:04 PM
            SMT is a dodo birdLinus Torvalds2013/05/12 02:22 PM
              Mediocre SMT implementations?Paul A. Clayton2013/05/12 05:06 PM
              SMT is a dodo birdmpx2013/05/12 06:13 PM
                Thanks for the actual research effort! (NT)Paul A. Clayton2013/05/13 05:43 AM
              How Does Silvermont Compare To A15?Ashraf Eassa2013/05/15 11:59 AM
                How Does Silvermont Compare To A15?Maynard Handley2013/05/15 04:08 PM
                  How Does Silvermont Compare To A15?TREZA2013/05/16 03:17 AM
                How Does Silvermont Compare To A15?Wilco2013/05/15 05:37 PM
                  How Does Silvermont Compare To A15?David Kanter2013/05/17 08:00 AM
                    How Does Silvermont Compare To A15?Exophase2013/05/17 08:52 AM
                      How Does Silvermont Compare To A15?David Kanter2013/05/17 09:38 PM
                        How Does Silvermont Compare To A15?Exophase2013/05/17 10:33 PM
                          FYI Tegra4 has A15 in it also, so 3 devices (NT)S. Rao2013/05/22 12:59 AM
                            FYI Tegra4 has A15 in it also, so 3 devicesMichael S2013/05/22 03:21 AM
                              FYI Tegra4 has A15 in it also, so 3 devicesS. Rao2013/05/22 10:06 AM
                        How Does Silvermont Compare To A15?Wilco2013/05/19 05:19 AM
                          How Does Silvermont Compare To A15?Patrick Chase2013/05/20 09:29 AM
                            Virtualization was also mostly server-orientedPaul A. Clayton2013/05/20 02:37 PM
                    How Does Silvermont Compare To A15?Wilco2013/05/17 12:22 PM
                      How Does Silvermont Compare To A15?David Kanter2013/05/17 09:29 PM
                        How Does Silvermont Compare To A15?Exophase2013/05/17 10:41 PM
                          How Does Silvermont Compare To A15?Gabriele Svelto2013/05/18 05:48 AM
                            How Does Silvermont Compare To A15?Exophase2013/05/18 09:57 AM
                          How Does Silvermont Compare To A15?David Kanter2013/05/18 08:02 AM
                            How Does Silvermont Compare To A15?Exophase2013/05/18 10:07 AM
                            How Does Silvermont Compare To A15?Wilco2013/05/18 12:04 PM
                        How Does Silvermont Compare To A15?anon2013/05/17 11:03 PM
                        How Does Silvermont Compare To A15?Maynard Handley2013/05/19 06:27 PM
                          How Does Silvermont Compare To A15?David Kanter2013/05/20 05:30 PM
                            How Does Silvermont Compare To A15?Exophase2013/05/20 06:06 PM
                              big.LITTLE and low-leakage processesPatrick Chase2013/05/20 09:26 PM
                                big.LITTLE and low-leakage processesExophase2013/05/20 09:56 PM
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                        Hard cores from ARM?Patrick Chase2013/05/19 12:38 PM
                  Architecture isn't everythingPatrick Chase2013/05/17 05:49 PM
                    Architecture isn't everythingBjörn R. Björnsson2013/05/17 06:34 PM
                      Architecture isn't everythingaaron spink2013/05/17 08:55 PM
                        Load delay slots need not be a problemPaul A. Clayton2013/05/18 05:41 AM
                          Load delay slots need not be a problemExophase2013/05/18 10:33 AM
                            Did cache misses disrupt load delay?Paul A. Clayton2013/05/18 03:48 PM
                              Did cache misses disrupt load delay?Exophase2013/05/18 07:45 PM
                            TI C6x load delaysPatrick Chase2013/05/19 04:19 PM
                              Hexagon documentation?David Kanter2013/05/23 11:19 AM
                                Hexagon documentation?Exophase2013/05/23 11:45 AM
                                Hexagon documentation?Patrick Chase2013/05/23 03:55 PM
                        Architecture isn't everythingLinus Torvalds2013/05/18 11:31 AM
                How Does Silvermont Compare To A15?David Kanter2013/05/17 08:12 AM
                  How Does Silvermont Compare To A15?Ashraf Eassa2013/05/18 09:06 PM
                    How Does Silvermont Compare To A15?Ashraf Eassa2013/05/18 09:06 PM
            SMT is a dodo birdDoug S2013/05/12 08:22 PM
              SMT is a dodo birdGabriele Svelto2013/05/13 12:53 AM
                SMT is a dodo birdMichael S2013/05/13 01:13 AM
              SMT is a dodo birdMichael S2013/05/13 01:30 AM
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    Two different RSBsPaul A. Clayton2013/05/06 09:35 PM
  Decode cacheanon2013/05/07 04:53 AM
    Decode cachenone2013/05/07 04:59 AM
      Decode cacheanon2013/05/07 06:08 AM
    There is also predecode information in IcachePaul A. Clayton2013/05/07 07:18 AM
      There is also predecode information in IcacheMaynard Handley2013/05/13 09:23 PM
    Decode cachenona2013/05/07 11:25 PM
  Silvermont architecture in-depth articlekashing ho2013/05/07 12:18 PM
    Silvermont architecture in-depth articleEduardoS2013/05/07 01:41 PM
      Silvermont architecture in-depth articleLinus Torvalds2013/05/07 03:07 PM
        Silvermont architecture in-depth articleEduardoS2013/05/07 07:18 PM
          Silvermont architecture in-depth articleY2013/05/08 04:23 AM
  Silvermont architecture in-depth articleChris Rodinis2013/05/22 03:56 PM
    Silvermont architecture in-depth articleDavid Kanter2013/05/23 01:17 AM
  Silvermont architecture in-depth articleSebastian Soeiro2013/05/28 09:00 AM
    Silvermont architecture in-depth articleDavid Kanter2013/05/28 12:14 PM
      Silvermont architecture in-depth articleSebastian Soeiro2013/05/28 12:45 PM
        Silvermont architecture in-depth articleRicardo B2013/05/28 03:58 PM
          Silvermont architecture in-depth articleSebastian Soeiro2013/05/28 04:27 PM
            Silvermont architecture in-depth articleRicardo B2013/05/29 02:41 PM
              Silvermont architecture in-depth articleSebastian Soeiro2013/05/29 10:16 PM
                Silvermont architecture in-depth articleRicardo B2013/05/30 08:05 AM
                  Silvermont architecture in-depth articleSebastian Soeiro2013/05/30 09:48 AM
                    Silvermont architecture in-depth articleRicardo B2013/05/30 11:18 AM
                      Silvermont architecture in-depth articleSebastian Soeiro2013/05/30 01:13 PM
                        Silvermont architecture in-depth articleSebastian Soeiro2013/05/30 03:39 PM
                          Silvermont architecture in-depth articleRicardo B2013/05/30 04:43 PM
                            Silvermont architecture in-depth articleSebastian Soeiro2013/05/30 07:52 PM
                              Silvermont architecture in-depth articleRicardo B2013/05/31 04:34 AM
                                Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 06:59 AM
                                  Silvermont architecture in-depth articleKlimax2013/05/31 07:15 AM
                                    Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 08:01 AM
                                      Silvermont architecture in-depth articlerwessel2013/05/31 10:59 AM
                                        Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 02:26 PM
                                          Silvermont architecture in-depth articlerwessel2013/05/31 03:11 PM
                                            Silvermont architecture in-depth articleSebastian Soeiro2013/06/03 09:51 AM
                                              Silvermont architecture in-depth articlerwessel2013/06/03 10:45 AM
                                              Silvermont architecture in-depth articlegallier22013/06/04 02:06 AM
                                                Silvermont architecture in-depth articleSebastian Soeiro2013/06/08 08:30 AM
                                  Silvermont architecture in-depth articleRicardo B2013/05/31 12:22 PM
                                    Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 02:22 PM
                                      Silvermont architecture in-depth articleDavid Kanter2013/05/31 03:08 PM
                                        Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 09:04 PM
                                          Silvermont architecture in-depth articlerwessel2013/05/31 09:53 PM
                                            Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 10:59 PM
                                              Silvermont architecture in-depth articleDavid Kanter2013/06/02 03:02 AM
                                                Silvermont architecture in-depth articleSebastian Soeiro2013/06/02 08:24 AM
                                                  Silvermont architecture in-depth articleDavid Kanter2013/06/02 11:10 PM
                                                    Silvermont architecture in-depth articleSebastian Soeiro2013/06/03 08:25 AM
                                              Silvermont architecture in-depth articlerwessel2013/06/03 12:09 AM
                                                Silvermont architecture in-depth articleSebastian Soeiro2013/06/03 09:59 AM
                                                  Silvermont architecture in-depth articlerwessel2013/06/03 10:51 AM
                                                    Silvermont architecture in-depth articleSebastian Soeiro2013/06/04 06:31 PM
                                      Silvermont architecture in-depth articlerwessel2013/05/31 03:20 PM
                                        Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 06:59 PM
                                          Silvermont architecture in-depth articlerwessel2013/05/31 09:02 PM
                                            Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 09:13 PM
                                            Quibbling on multithreadingPaul A. Clayton2013/06/01 10:11 AM
                                              Quibbling on multithreadingrwessel2013/06/02 11:54 PM
                                                Exploiting for SMT was my "contribution"Paul A. Clayton2013/06/03 04:53 AM
                                            Silvermont architecture in-depth articleMichael S2013/06/01 10:49 AM
                        Silvermont architecture in-depth articleRicardo B2013/05/30 04:41 PM
                          Didn't notice how this was to be organized...Sebastian Soeiro2013/05/30 07:55 PM
          Silvermont, not Saltwell? (NT)papapapa2013/05/28 04:33 PM
            Of course. Not enough sleep. (NT)Ricardo B2013/05/29 02:27 PM
  No out-of-order in FP cluster of silvermont?anon2013/06/28 03:27 AM
    No out-of-order in FP cluster of silvermont?Michael S2013/06/28 04:52 AM
      No out-of-order in FP cluster of silvermont?Exophase2013/06/28 01:54 PM
        No out-of-order in FP cluster of silvermont?Michael S2013/06/29 11:21 AM
          No out-of-order in FP cluster of silvermont?Exophase2013/06/29 09:07 PM
      No out-of-order in FP cluster of silvermont?Linus Torvalds2013/06/29 12:22 PM
        No out-of-order in FP cluster of silvermont?anon2013/06/29 05:26 PM
          No out-of-order in FP cluster of silvermont?EduardoS2013/06/29 06:50 PM
            No out-of-order in FP cluster of silvermont?anon2013/06/29 09:15 PM
              No out-of-order in FP cluster of silvermont?EduardoS2013/06/29 09:31 PM
                No out-of-order in FP cluster of silvermont?anon2013/06/30 02:53 AM
                  No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 05:24 AM
                    No out-of-order in FP cluster of silvermont?anon2013/06/30 10:41 AM
                      No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 01:26 PM
                        No out-of-order in FP cluster of silvermont?anon2013/07/01 12:32 AM
                          No out-of-order in FP cluster of silvermont?EduardoS2013/07/01 05:40 PM
                            No out-of-order in FP cluster of silvermont?anon2013/07/01 06:44 PM
                            No out-of-order in FP cluster of silvermont?Michael S2013/07/02 05:40 AM
                              No out-of-order in FP cluster of silvermont?Exophase2013/07/02 09:03 AM
                              No out-of-order in FP cluster of silvermont?EduardoS2013/07/02 05:20 PM
                          No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 09:25 AM
                      No out-of-order in FP cluster of silvermont?Etienne2013/07/02 04:36 AM
                        No out-of-order in FP cluster of silvermont?anon2013/07/02 07:13 AM
                          No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 10:03 AM
                            No out-of-order in FP cluster of silvermont?anon2013/07/02 04:12 PM
                              No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 04:43 PM
                                No out-of-order in FP cluster of silvermont?anon2013/07/02 05:47 PM
                                  No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 07:36 PM
                                    No out-of-order in FP cluster of silvermont?anon2013/07/02 09:03 PM
                                      No out-of-order in FP cluster of silvermont?Symmetry2013/07/03 07:14 AM
                                        No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/03 09:04 PM
                                          No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/04 03:23 AM
                        No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 10:01 AM
                          No out-of-order in FP cluster of silvermont?Etienne2013/07/03 03:26 AM
                            layer 2 cache behaviourEtienne2013/07/05 03:14 AM
                              layer 2 cache behaviourMichael S2013/07/05 06:41 AM
                                layer 2 cache behaviourEtienne2013/07/05 09:15 AM
                              layer 2 cache behaviourPatrick Chase2013/07/05 11:37 AM
                                layer 2 cache behaviourMichael S2013/07/06 10:57 AM
                                  layer 2 cache behaviourPatrick Chase2013/07/06 12:08 PM
                                    layer 2 cache behaviourPatrick Chase2013/07/06 12:19 PM
                                    layer 2 cache behaviourEtienne2013/07/08 03:10 AM
                                      layer 2 cache behaviourPatrick Chase2013/07/08 10:02 AM
                                  layer 2 cache behaviourPatrick Chase2013/07/06 02:15 PM
                                  layer 2 cache behaviourUngo2013/07/09 03:24 PM
                      No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 08:43 AM
                  No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 08:34 AM
                    No out-of-order in FP cluster of silvermont?anon2013/07/02 04:15 PM
            No out-of-order in FP cluster of silvermont?none2013/06/30 05:03 AM
              No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 05:45 AM
                No out-of-order in FP cluster of silvermont?none2013/06/30 06:28 AM
                  No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 01:27 PM
        No out-of-order in FP cluster of silvermont?x2013/06/30 03:54 AM
          No out-of-order in FP cluster of silvermont?Foo_2013/06/30 06:15 AM
        No out-of-order in FP cluster of silvermont?rwessel2013/06/30 10:11 PM
          No out-of-order in FP cluster of silvermont?Linus Torvalds2013/07/01 01:40 PM
            No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 10:35 AM
              No out-of-order in FP cluster of silvermont?Linus Torvalds2013/07/02 11:18 AM
            FPU in integer codes2013/07/02 11:38 AM
              FPU in integer codesPatrick Chase2013/07/02 11:56 AM
              FPU in integer codesLinus Torvalds2013/07/02 12:12 PM
                FPU in integer codesPatrick Chase2013/07/02 12:34 PM
                  FPU in integer codesLinus Torvalds2013/07/02 01:55 PM
        No out-of-order in FP cluster of silvermont?2013/06/30 11:42 PM
          No out-of-order in FP cluster of silvermont?bakaneko2013/07/03 03:54 AM
        What about integer SIMD?Exophase2013/07/01 12:44 AM
          What about integer SIMD?anon2013/07/01 01:45 AM
            What about integer SIMD?Michael S2013/07/01 08:57 AM
              What about integer SIMD?rwessel2013/07/01 03:39 PM
                What about integer SIMD?Michael S2013/07/01 04:11 PM
                  What about integer SIMD?EduardoS2013/07/01 06:04 PM
                    What about integer SIMD?Michael S2013/07/02 12:32 AM
          What about integer SIMD?hi2013/07/01 08:15 AM
            What about integer SIMD?Exophase2013/07/01 10:50 AM
            What about integer SIMD?David Kanter2013/07/02 01:20 PM
              What about integer SIMD?hi2013/07/02 03:48 PM
                What about integer SIMD?David Kanter2013/07/04 03:19 PM
  Silvermont architecture in-depth articleSebastian Soeiro2013/07/30 09:34 AM
    TLBs are caches of page tablesPaul A. Clayton2013/07/30 11:03 AM
      TLBs are caches of page tablesSebastian Soeiro2013/07/30 01:18 PM
        TLBs are caches of page tablesPaul A. Clayton2013/07/30 03:59 PM
          TLBs are caches of page tablesSebastian Soeiro2013/07/30 05:27 PM
            TLBs are caches of page tablesrwessel2013/07/30 07:01 PM
              TLBs are caches of page tablesSebastian Soeiro2013/07/31 02:15 PM
                Floorplan images show physical locationsPaul A. Clayton2013/07/31 04:11 PM
                  Floorplan images show physical locationsSebastian Soeiro2013/07/31 09:12 PM
                    Floorplan images show physical locationsrwessel2013/08/01 12:21 AM
                      Floorplan images show physical locationsSebastian Soeiro2013/08/02 12:58 PM
                        Floorplan images show physical locationsAntti-Ville Tuunainen2013/08/02 02:09 PM
                        Floorplan images show physical locationsStubabe2013/08/02 07:49 PM
                          Floorplan images show physical locationsSebastian Soeiro2013/08/03 08:23 AM
                            Floorplan images show physical locationsrwessel2013/08/03 11:16 PM
                            Floorplan images show physical locationsMelody Speer2013/08/04 04:11 AM
                              Floorplan images show physical locationsSebastian Soeiro2013/08/04 05:42 PM
                                Floorplan images show physical locationsrwessel2013/08/04 10:58 PM
                                  Floorplan images show physical locationsSebastian Soeiro2013/08/07 03:33 PM
                                    Floorplan images show physical locationsrwessel2013/08/08 01:03 PM
                                      Floorplan images show physical locationsSebastian Soeiro2013/08/11 09:20 AM
                                        Page tables are set up by the OSPaul A. Clayton2013/08/11 01:25 PM
                                          Page tables are set up by the OSSebastian Soeiro2013/08/16 08:43 PM
                                            Multilevel page table formatPaul A. Clayton2013/08/17 11:18 AM
                                              Multilevel page table formatSebastian Soeiro2013/08/19 03:28 PM
                                                Multilevel page table formatrwessel2013/08/20 12:08 AM
                                                  Multilevel page table formatSebastian Soeiro2013/08/22 04:52 PM
                                                    Multilevel page table formatTREZA2013/08/22 05:30 PM
                                                    Multilevel page table formatrwessel2013/08/23 10:58 PM
                                                      Multilevel page table formatSebastian Soeiro2013/08/25 08:20 AM
                TLBs are caches of page tablesrwessel2013/08/01 12:41 AM
                  TLBs are caches of page tablesSebastian Soeiro2013/08/02 12:51 PM
                    TLBs are caches of page tablesrwessel2013/08/02 06:55 PM
  Silvermont instruction schedulingHugo Décharnes2013/10/02 03:25 AM
    Silvermont instruction schedulingMichael S2013/10/02 04:29 AM
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