Silvermont architecture in-depth article

Article: Silvermont, Intel's Low Power Architecture
By: rwessel (robertwessel.delete@this.yahoo.com), May 31, 2013 8:53 pm
Room: Moderated Discussions
Sebastian Soeiro (sebastian_2896.delete@this.hotmail.com) on May 31, 2013 9:04 pm wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on May 31, 2013 3:08 pm wrote:
> > Sebastian Soeiro (sebastian_2896.delete@this.hotmail.com) on May 31, 2013 2:22 pm wrote:
> > > Ricardo B (ricardo.b.delete@this.xxxxx.xx) on May 31, 2013 12:22 pm wrote:
> > > > Sebastian Soeiro (sebastian_2896.delete@this.hotmail.com) on May 31, 2013 6:59 am wrote:
> > > >
> > > > > The array example definitely helped. Though one more about AGU's; say a AGU is given an
> > > > > instruction to calculate the virtual address of (array+4), and it does so successfully.
> > > > > Where would the result of the virtual address be stored, and how would it be used?
> > > >
> > > > Usually, the virtual address calculated by the AGU is forwarded directly
> > > > to the DTLB and L1 D$ to be used as an address for a store/load.
> > > >
> > > > It's also possible to store the address calculated by the AGU into a register for other uses.
> > > >
> > > > > - Sorry, I still don't quite understand how multi-threading works. If there are two programs,
> > > > > one of each using one thread, how does a single execution unit perform as two?
> > > >
> > > > For example, while an Ivy Bridge CPU can in theory sustain 6 µOPs per clock, in practice most
> > > > software runs at ~1 µOP per clock, due to instruction dependencies and other things.
> > > >
> > > > There is thus, lots of free time to execute instructions for a second thread.
> > > >
> > > >
> > >
> > > Thanks again for the reply!
> > >
> > > - Oh, so the AGU is sort of like a "decoder" for store and load operations? So hopefully my understanding
> > > is correct now;
> >
> > It's not a decoder. It calculates the address, based on the instructions used in the code. Instructions
> > have very different addressing modes, and the AGU needs to be able to handle all of them. Most address
> > calculations are simple, but they can be quite complex, involving multiplication and addition.
> >
> > > The scheduler gives a location for the AGU to decode, which can either be simple
> > > (EDX1) or complex (EDX2+2/5^65%4),
> >
> > It's specified by an instruction, not the scheduler. It might get held in the scheduler temporarily.
> > Honestly, you might find it beneficial to read some of my other
> > articles, such as http://www.realworldtech.com/barcelona/
> > they have a good narration of the pipeline.
> >
> > >and once it figures out what the virtual address of this location
> > > is, it sends the request to the DTLB, which performs a look up of this virtual address, which finds
> > > where the data is,
> >
> > That's correct, the DTLB converts from virtual to physical addresses.
> >
> > >and then requests it from wherever it is through the caches into the data cache
> > > for the execution units to utilize? Hopefully I've gotten it right by now...
> >
> > It requests that address from the cache and loads it into a register. Which is why we call it a load.
> >
> > Stores work rather differently, since it is moving data from a register to the memory.
> >
> > David
>
> Hello David, thanks for taking the time to reply to my post; I definitely appreciate it!
>
> - I know that the AGU is not a decoder; though for some reason, my mind likes to think of the equation
> that the virtual addresses come in are "in code" and that the AGU clarifies where the destination really
> is. Though, to my understanding; it is really like an ALU that takes the request for a virtual address
> and then clarifies where this address is (not physically, but virtually.) Hopefully this is correct.
>
> - Ah, to clarify what I was trying to say previously; I mean to say that the instruction declares what
> operands it needs, and requests the operands needed by the AGU, where the AGU calculates the requests
> for these operands, and then the DTLB looks up the virtual address to find out where the data is in
> physical memory, (and here is where my understanding gets shaky) which once the address is found (through
> whatever cache escalations is needed), the operands are sent through the load/store units, through
> the AGU and back into the scheduler for the instruction to be passed onto the ALU to calculate? Or
> atleast thats how Barcelona looks like; though I'm sure I'm wrong here; why would operands be sent
> through an AGU?


The operand itself would never go through the AGU, rather the generated address is passed to the load/store unit (often the AGU is part of that), and once the load completes, the operand is forwarded to the execution unit where the dispatched instruction is waiting for it. Exactly how that happens depends a great deal on the microarchitecture. On a simple in-order design the pipeline may simply be stalled waiting for the load unit to present the single outstanding operand. In an OoO design, a rather more complicated network will exist to get the operand to the instruction (micro-op) needing it, where ever that's happened to end up waiting. Once the instruction has all of its operands, it can then be executed.

Things are a bit different on the store side, as the operand is usually available pretty early (it's a store, after all, you already have the operand), and the store, along with the address, can but pushed quickly into the store buffer, and that can then complete independently of the instruction stream. A critical issue is maintaining a coherent and properly sequential view of memory even if the actual (physical) stores and loads are not happening in the architected order. It's not so bad within a single processor, since the store buffer can watch for other memory accesses, and jump in when it has a pending store. But since memory accesses are visible to other processors (and I/O devices), great effort must be taken to ensure that those other devices only see memory accesses in the architected order, or you'll break every multithreaded program in sight.
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                        quad-core since Nov 2006RichardC2013/05/13 02:48 AM
                          quad-core since Nov 2006Jukka Larja2013/05/14 10:34 AM
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                          SMT is a dodo birdMichael S2013/05/13 02:50 AM
                            SMT is a dodo birdRicardo B2013/05/13 05:13 AM
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                               4C/4T 4.0GHz was significantly faster than 4C/4T 3.8GHz??Mark Roulo2013/05/14 04:37 PM
                                 4C/4T 4.0GHz was significantly faster than 4C/4T 3.8GHz??RichardC2013/05/14 04:54 PM
                                  Thanks. Mark Roulo2013/05/14 05:05 PM
                                   4C/4T 4.0GHz was significantly faster than 4C/4T 3.8GHz??Exophase2013/05/14 07:10 PM
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                                       More tests of HT and gamesRichardC2013/05/15 02:26 AM
                                         More tests of HT and gamesExophase2013/05/15 05:43 AM
                                           More tests of HT and gamesMichael S2013/05/15 11:35 AM
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                          SMT is a dodo birdJukka Larja2013/05/15 08:02 AM
                        SMT is a dodo birdPatrick Chase2013/05/17 08:43 AM
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                          SMT is a dodo birdBrett2013/05/17 06:26 PM
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                  SMT is a dodo birdRichardC2013/05/12 05:57 AM
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                SMT is a dodo birdStubabe2013/05/14 11:09 AM
                  SMT is a dodo birdRichardC2013/05/14 12:43 PM
                    SMT is a dodo birdRicardo B2013/05/14 02:00 PM
                      SMT is a dodo birdRichardC2013/05/14 05:27 PM
                        SMT is a dodo birdRicardo B2013/05/15 02:50 AM
                          SMT is a dodo birdRichardC2013/05/15 07:53 AM
                            SMT is a dodo birdRicardo B2013/05/15 08:31 AM
                              SMT is a dodo birdRichardC2013/05/15 10:13 AM
                                SMT is a dodo birdRicardo B2013/05/15 11:43 AM
                                  SMT is a dodo birdRichardC2013/05/15 12:15 PM
                                    SMT is a dodo birdRicardo B2013/05/15 12:40 PM
                                      SMT is a dodo birdRichardC2013/05/15 01:00 PM
                                        SMT is a dodo birdMaynard Handley2013/05/15 02:55 PM
                                        SMT is a dodo birdJouni Osmala2013/05/16 02:16 AM
                    SMT is a dodo birdStubabe2013/05/16 10:54 AM
                  Using the available die areaDoug S2013/05/14 04:51 PM
                    Using the available die areaRicardo B2013/05/15 03:15 AM
                      Using the available die areaStubabe2013/05/16 10:26 AM
                        Using the available die areaRicardo B2013/05/16 01:05 PM
      SMT is a dodo birdmpx2013/05/10 10:51 PM
        SMT is a dodo birdFoo_2013/05/11 04:21 AM
          SMT is a dodo birdEduardoS2013/05/11 08:28 AM
        SMT is a dodo birdDoug S2013/05/11 09:49 AM
          SMT is a dodo birdmpx2013/05/12 11:04 AM
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              SMT is a dodo birdmpx2013/05/12 05:13 PM
                Thanks for the actual research effort! (NT)Paul A. Clayton2013/05/13 04:43 AM
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                  How Does Silvermont Compare To A15?TREZA2013/05/16 02:17 AM
                How Does Silvermont Compare To A15?Wilco2013/05/15 04:37 PM
                  How Does Silvermont Compare To A15?David Kanter2013/05/17 07:00 AM
                    How Does Silvermont Compare To A15?Exophase2013/05/17 07:52 AM
                      How Does Silvermont Compare To A15?David Kanter2013/05/17 08:38 PM
                        How Does Silvermont Compare To A15?Exophase2013/05/17 09:33 PM
                          FYI Tegra4 has A15 in it also, so 3 devices (NT)S. Rao2013/05/21 11:59 PM
                            FYI Tegra4 has A15 in it also, so 3 devicesMichael S2013/05/22 02:21 AM
                              FYI Tegra4 has A15 in it also, so 3 devicesS. Rao2013/05/22 09:06 AM
                        How Does Silvermont Compare To A15?Wilco2013/05/19 04:19 AM
                          How Does Silvermont Compare To A15?Patrick Chase2013/05/20 08:29 AM
                            Virtualization was also mostly server-orientedPaul A. Clayton2013/05/20 01:37 PM
                    How Does Silvermont Compare To A15?Wilco2013/05/17 11:22 AM
                      How Does Silvermont Compare To A15?David Kanter2013/05/17 08:29 PM
                        How Does Silvermont Compare To A15?Exophase2013/05/17 09:41 PM
                          How Does Silvermont Compare To A15?Gabriele Svelto2013/05/18 04:48 AM
                            How Does Silvermont Compare To A15?Exophase2013/05/18 08:57 AM
                          How Does Silvermont Compare To A15?David Kanter2013/05/18 07:02 AM
                            How Does Silvermont Compare To A15?Exophase2013/05/18 09:07 AM
                            How Does Silvermont Compare To A15?Wilco2013/05/18 11:04 AM
                        How Does Silvermont Compare To A15?anon2013/05/17 10:03 PM
                        How Does Silvermont Compare To A15?Maynard Handley2013/05/19 05:27 PM
                          How Does Silvermont Compare To A15?David Kanter2013/05/20 04:30 PM
                            How Does Silvermont Compare To A15?Exophase2013/05/20 05:06 PM
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                  Architecture isn't everythingPatrick Chase2013/05/17 04:49 PM
                    Architecture isn't everythingBjörn R. Björnsson2013/05/17 05:34 PM
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                          Load delay slots need not be a problemExophase2013/05/18 09:33 AM
                            Did cache misses disrupt load delay?Paul A. Clayton2013/05/18 02:48 PM
                              Did cache misses disrupt load delay?Exophase2013/05/18 06:45 PM
                            TI C6x load delaysPatrick Chase2013/05/19 03:19 PM
                              Hexagon documentation?David Kanter2013/05/23 10:19 AM
                                Hexagon documentation?Exophase2013/05/23 10:45 AM
                                Hexagon documentation?Patrick Chase2013/05/23 02:55 PM
                        Architecture isn't everythingLinus Torvalds2013/05/18 10:31 AM
                How Does Silvermont Compare To A15?David Kanter2013/05/17 07:12 AM
                  How Does Silvermont Compare To A15?Ashraf Eassa2013/05/18 08:06 PM
                    How Does Silvermont Compare To A15?Ashraf Eassa2013/05/18 08:06 PM
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              SMT is a dodo birdMichael S2013/05/13 12:30 AM
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    Decode cachenone2013/05/07 03:59 AM
      Decode cacheanon2013/05/07 05:08 AM
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                    Silvermont architecture in-depth articleRicardo B2013/05/30 10:18 AM
                      Silvermont architecture in-depth articleSebastian Soeiro2013/05/30 12:13 PM
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                          Silvermont architecture in-depth articleRicardo B2013/05/30 03:43 PM
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                              Silvermont architecture in-depth articleRicardo B2013/05/31 03:34 AM
                                Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 05:59 AM
                                  Silvermont architecture in-depth articleKlimax2013/05/31 06:15 AM
                                    Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 07:01 AM
                                      Silvermont architecture in-depth articlerwessel2013/05/31 09:59 AM
                                        Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 01:26 PM
                                          Silvermont architecture in-depth articlerwessel2013/05/31 02:11 PM
                                            Silvermont architecture in-depth articleSebastian Soeiro2013/06/03 08:51 AM
                                              Silvermont architecture in-depth articlerwessel2013/06/03 09:45 AM
                                              Silvermont architecture in-depth articlegallier22013/06/04 01:06 AM
                                                Silvermont architecture in-depth articleSebastian Soeiro2013/06/08 07:30 AM
                                  Silvermont architecture in-depth articleRicardo B2013/05/31 11:22 AM
                                    Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 01:22 PM
                                      Silvermont architecture in-depth articleDavid Kanter2013/05/31 02:08 PM
                                        Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 08:04 PM
                                          Silvermont architecture in-depth articlerwessel2013/05/31 08:53 PM
                                            Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 09:59 PM
                                              Silvermont architecture in-depth articleDavid Kanter2013/06/02 02:02 AM
                                                Silvermont architecture in-depth articleSebastian Soeiro2013/06/02 07:24 AM
                                                  Silvermont architecture in-depth articleDavid Kanter2013/06/02 10:10 PM
                                                    Silvermont architecture in-depth articleSebastian Soeiro2013/06/03 07:25 AM
                                              Silvermont architecture in-depth articlerwessel2013/06/02 11:09 PM
                                                Silvermont architecture in-depth articleSebastian Soeiro2013/06/03 08:59 AM
                                                  Silvermont architecture in-depth articlerwessel2013/06/03 09:51 AM
                                                    Silvermont architecture in-depth articleSebastian Soeiro2013/06/04 05:31 PM
                                      Silvermont architecture in-depth articlerwessel2013/05/31 02:20 PM
                                        Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 05:59 PM
                                          Silvermont architecture in-depth articlerwessel2013/05/31 08:02 PM
                                            Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 08:13 PM
                                            Quibbling on multithreadingPaul A. Clayton2013/06/01 09:11 AM
                                              Quibbling on multithreadingrwessel2013/06/02 10:54 PM
                                                Exploiting for SMT was my "contribution"Paul A. Clayton2013/06/03 03:53 AM
                                            Silvermont architecture in-depth articleMichael S2013/06/01 09:49 AM
                        Silvermont architecture in-depth articleRicardo B2013/05/30 03:41 PM
                          Didn't notice how this was to be organized...Sebastian Soeiro2013/05/30 06:55 PM
          Silvermont, not Saltwell? (NT)papapapa2013/05/28 03:33 PM
            Of course. Not enough sleep. (NT)Ricardo B2013/05/29 01:27 PM
  No out-of-order in FP cluster of silvermont?anon2013/06/28 02:27 AM
    No out-of-order in FP cluster of silvermont?Michael S2013/06/28 03:52 AM
      No out-of-order in FP cluster of silvermont?Exophase2013/06/28 12:54 PM
        No out-of-order in FP cluster of silvermont?Michael S2013/06/29 10:21 AM
          No out-of-order in FP cluster of silvermont?Exophase2013/06/29 08:07 PM
      No out-of-order in FP cluster of silvermont?Linus Torvalds2013/06/29 11:22 AM
        No out-of-order in FP cluster of silvermont?anon2013/06/29 04:26 PM
          No out-of-order in FP cluster of silvermont?EduardoS2013/06/29 05:50 PM
            No out-of-order in FP cluster of silvermont?anon2013/06/29 08:15 PM
              No out-of-order in FP cluster of silvermont?EduardoS2013/06/29 08:31 PM
                No out-of-order in FP cluster of silvermont?anon2013/06/30 01:53 AM
                  No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 04:24 AM
                    No out-of-order in FP cluster of silvermont?anon2013/06/30 09:41 AM
                      No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 12:26 PM
                        No out-of-order in FP cluster of silvermont?anon2013/06/30 11:32 PM
                          No out-of-order in FP cluster of silvermont?EduardoS2013/07/01 04:40 PM
                            No out-of-order in FP cluster of silvermont?anon2013/07/01 05:44 PM
                            No out-of-order in FP cluster of silvermont?Michael S2013/07/02 04:40 AM
                              No out-of-order in FP cluster of silvermont?Exophase2013/07/02 08:03 AM
                              No out-of-order in FP cluster of silvermont?EduardoS2013/07/02 04:20 PM
                          No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 08:25 AM
                      No out-of-order in FP cluster of silvermont?Etienne2013/07/02 03:36 AM
                        No out-of-order in FP cluster of silvermont?anon2013/07/02 06:13 AM
                          No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 09:03 AM
                            No out-of-order in FP cluster of silvermont?anon2013/07/02 03:12 PM
                              No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 03:43 PM
                                No out-of-order in FP cluster of silvermont?anon2013/07/02 04:47 PM
                                  No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 06:36 PM
                                    No out-of-order in FP cluster of silvermont?anon2013/07/02 08:03 PM
                                      No out-of-order in FP cluster of silvermont?Symmetry2013/07/03 06:14 AM
                                        No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/03 08:04 PM
                                          No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/04 02:23 AM
                        No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 09:01 AM
                          No out-of-order in FP cluster of silvermont?Etienne2013/07/03 02:26 AM
                            layer 2 cache behaviourEtienne2013/07/05 02:14 AM
                              layer 2 cache behaviourMichael S2013/07/05 05:41 AM
                                layer 2 cache behaviourEtienne2013/07/05 08:15 AM
                              layer 2 cache behaviourPatrick Chase2013/07/05 10:37 AM
                                layer 2 cache behaviourMichael S2013/07/06 09:57 AM
                                  layer 2 cache behaviourPatrick Chase2013/07/06 11:08 AM
                                    layer 2 cache behaviourPatrick Chase2013/07/06 11:19 AM
                                    layer 2 cache behaviourEtienne2013/07/08 02:10 AM
                                      layer 2 cache behaviourPatrick Chase2013/07/08 09:02 AM
                                  layer 2 cache behaviourPatrick Chase2013/07/06 01:15 PM
                                  layer 2 cache behaviourUngo2013/07/09 02:24 PM
                      No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 07:43 AM
                  No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 07:34 AM
                    No out-of-order in FP cluster of silvermont?anon2013/07/02 03:15 PM
            No out-of-order in FP cluster of silvermont?none2013/06/30 04:03 AM
              No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 04:45 AM
                No out-of-order in FP cluster of silvermont?none2013/06/30 05:28 AM
                  No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 12:27 PM
        No out-of-order in FP cluster of silvermont?x2013/06/30 02:54 AM
          No out-of-order in FP cluster of silvermont?Foo_2013/06/30 05:15 AM
        No out-of-order in FP cluster of silvermont?rwessel2013/06/30 09:11 PM
          No out-of-order in FP cluster of silvermont?Linus Torvalds2013/07/01 12:40 PM
            No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 09:35 AM
              No out-of-order in FP cluster of silvermont?Linus Torvalds2013/07/02 10:18 AM
            FPU in integer codes2013/07/02 10:38 AM
              FPU in integer codesPatrick Chase2013/07/02 10:56 AM
              FPU in integer codesLinus Torvalds2013/07/02 11:12 AM
                FPU in integer codesPatrick Chase2013/07/02 11:34 AM
                  FPU in integer codesLinus Torvalds2013/07/02 12:55 PM
        No out-of-order in FP cluster of silvermont?2013/06/30 10:42 PM
          No out-of-order in FP cluster of silvermont?bakaneko2013/07/03 02:54 AM
        What about integer SIMD?Exophase2013/06/30 11:44 PM
          What about integer SIMD?anon2013/07/01 12:45 AM
            What about integer SIMD?Michael S2013/07/01 07:57 AM
              What about integer SIMD?rwessel2013/07/01 02:39 PM
                What about integer SIMD?Michael S2013/07/01 03:11 PM
                  What about integer SIMD?EduardoS2013/07/01 05:04 PM
                    What about integer SIMD?Michael S2013/07/01 11:32 PM
          What about integer SIMD?hi2013/07/01 07:15 AM
            What about integer SIMD?Exophase2013/07/01 09:50 AM
            What about integer SIMD?David Kanter2013/07/02 12:20 PM
              What about integer SIMD?hi2013/07/02 02:48 PM
                What about integer SIMD?David Kanter2013/07/04 02:19 PM
  Silvermont architecture in-depth articleSebastian Soeiro2013/07/30 08:34 AM
    TLBs are caches of page tablesPaul A. Clayton2013/07/30 10:03 AM
      TLBs are caches of page tablesSebastian Soeiro2013/07/30 12:18 PM
        TLBs are caches of page tablesPaul A. Clayton2013/07/30 02:59 PM
          TLBs are caches of page tablesSebastian Soeiro2013/07/30 04:27 PM
            TLBs are caches of page tablesrwessel2013/07/30 06:01 PM
              TLBs are caches of page tablesSebastian Soeiro2013/07/31 01:15 PM
                Floorplan images show physical locationsPaul A. Clayton2013/07/31 03:11 PM
                  Floorplan images show physical locationsSebastian Soeiro2013/07/31 08:12 PM
                    Floorplan images show physical locationsrwessel2013/07/31 11:21 PM
                      Floorplan images show physical locationsSebastian Soeiro2013/08/02 11:58 AM
                        Floorplan images show physical locationsAntti-Ville Tuunainen2013/08/02 01:09 PM
                        Floorplan images show physical locationsStubabe2013/08/02 06:49 PM
                          Floorplan images show physical locationsSebastian Soeiro2013/08/03 07:23 AM
                            Floorplan images show physical locationsrwessel2013/08/03 10:16 PM
                            Floorplan images show physical locationsMelody Speer2013/08/04 03:11 AM
                              Floorplan images show physical locationsSebastian Soeiro2013/08/04 04:42 PM
                                Floorplan images show physical locationsrwessel2013/08/04 09:58 PM
                                  Floorplan images show physical locationsSebastian Soeiro2013/08/07 02:33 PM
                                    Floorplan images show physical locationsrwessel2013/08/08 12:03 PM
                                      Floorplan images show physical locationsSebastian Soeiro2013/08/11 08:20 AM
                                        Page tables are set up by the OSPaul A. Clayton2013/08/11 12:25 PM
                                          Page tables are set up by the OSSebastian Soeiro2013/08/16 07:43 PM
                                            Multilevel page table formatPaul A. Clayton2013/08/17 10:18 AM
                                              Multilevel page table formatSebastian Soeiro2013/08/19 02:28 PM
                                                Multilevel page table formatrwessel2013/08/19 11:08 PM
                                                  Multilevel page table formatSebastian Soeiro2013/08/22 03:52 PM
                                                    Multilevel page table formatTREZA2013/08/22 04:30 PM
                                                    Multilevel page table formatrwessel2013/08/23 09:58 PM
                                                      Multilevel page table formatSebastian Soeiro2013/08/25 07:20 AM
                TLBs are caches of page tablesrwessel2013/07/31 11:41 PM
                  TLBs are caches of page tablesSebastian Soeiro2013/08/02 11:51 AM
                    TLBs are caches of page tablesrwessel2013/08/02 05:55 PM
  Silvermont instruction schedulingHugo Décharnes2013/10/02 02:25 AM
    Silvermont instruction schedulingMichael S2013/10/02 03:29 AM
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