By: David Kanter (email@example.com), June 2, 2013 2:02 am
Room: Moderated Discussions
> - So there is a load/store unit that is included in the AGU's in the diagrams? Operands flow through these
> units? That makes sense; but one thing: how do these load/store units get the operands to the execution
> units? Are they directly linked or do they go through one of the other scheduler/buffers above?
The 'load store unit' typically includes:
3. Access to data cache (for loads)
4. Store buffer (for stores)
For a load, once the address is calculated by the AGU, the rest happens automatically with the end result being that a data value is moved from memory to a register.