David Kanter (dkanter.delete@this.realworldtech.com) on June 2, 2013 3:02 am wrote:
>
> > - So there is a load/store unit that is included in the AGU's in the diagrams? Operands flow through these
> > units? That makes sense; but one thing: how do these load/store units get the operands to the execution
> > units? Are they directly linked or do they go through one of the other scheduler/buffers above?
>
> The 'load store unit' typically includes:
>
> 1. AGU
> 2. DTLB
> 3. Access to data cache (for loads)
> 4. Store buffer (for stores)
>
> For a load, once the address is calculated by the AGU, the rest happens automatically
> with the end result being that a data value is moved from memory to a register.
>
> DK

Thank you very much, David.

So the AGU on the diagram has direct access to the necessary registers?

- Sebastian