By: EduardoS (no.delete@this.spam.com), July 1, 2013 5:40 pm
Room: Moderated Discussions
anon (anon.delete@this.anon.com) on July 1, 2013 12:32 am wrote:
> None of your post provided any other real evidence or logic.
Maybe bacause you do not understand math...
> Intel doubled SIMD width in SandyBridge and had to redesign the pipeline to be PRF-based.
>
> So you think going to a PRF was pretty easy change?
First, Intel didn't had to go PRF, they choose to go this way, AMD went PRF even without 256 bits registers, hell, AMD went PRF with 64 bits registers!
In Intel case a simple doubling of width would work, but they decided that also going to PRF would be more benefical, as they decided about the uop cahce, etc.
> Words to that effect. I was paraphrasing.
You were puting words in my month.
> No, I'm asking you.
And I answeared you, but you ignored the answear.
> No, you can have a memory latency benchmark which fits in L4. Or a particular workload which just manages
> to fit.
And why those wouldn't fit L3?
> No, why should I? Do you have any die shots for your assertion that it is free or very cheap?
You said A15 FPU were expensive, not me, stop putig words in my month.
> But you said that designers and consumers prefer to pay for things which are
> not relevant to their workloads.
I said two things, you ignored one and are pushing the other to insane levels
> If high FLOPS is one of those things, moving
> to a GPU-like core would be a cheap way to win useless benchmarks.
Or just use GPUs, BTW, winning useless bennchmarks is nice, paying to win them are not, why don't you re-read the other half of my original post?
Forgot it, you won't read, you are just a useless troll.
> None of your post provided any other real evidence or logic.
Maybe bacause you do not understand math...
> Intel doubled SIMD width in SandyBridge and had to redesign the pipeline to be PRF-based.
>
> So you think going to a PRF was pretty easy change?
First, Intel didn't had to go PRF, they choose to go this way, AMD went PRF even without 256 bits registers, hell, AMD went PRF with 64 bits registers!
In Intel case a simple doubling of width would work, but they decided that also going to PRF would be more benefical, as they decided about the uop cahce, etc.
> Words to that effect. I was paraphrasing.
You were puting words in my month.
> No, I'm asking you.
And I answeared you, but you ignored the answear.
> No, you can have a memory latency benchmark which fits in L4. Or a particular workload which just manages
> to fit.
And why those wouldn't fit L3?
> No, why should I? Do you have any die shots for your assertion that it is free or very cheap?
You said A15 FPU were expensive, not me, stop putig words in my month.
> But you said that designers and consumers prefer to pay for things which are
> not relevant to their workloads.
I said two things, you ignored one and are pushing the other to insane levels
> If high FLOPS is one of those things, moving
> to a GPU-like core would be a cheap way to win useless benchmarks.
Or just use GPUs, BTW, winning useless bennchmarks is nice, paying to win them are not, why don't you re-read the other half of my original post?
Forgot it, you won't read, you are just a useless troll.
