By: anon (anon.delete@this.anon.com), July 1, 2013 6:44 pm
Room: Moderated Discussions
EduardoS (no.delete@this.spam.com) on July 1, 2013 5:40 pm wrote:
> anon (anon.delete@this.anon.com) on July 1, 2013 12:32 am wrote:
> > None of your post provided any other real evidence or logic.
>
> Maybe bacause you do not understand math...
You did not present any math.
>
> > Intel doubled SIMD width in SandyBridge and had to redesign the pipeline to be PRF-based.
> >
> > So you think going to a PRF was pretty easy change?
>
> First, Intel didn't had to go PRF, they choose to go this way, AMD went PRF
> even without 256 bits registers, hell, AMD went PRF with 64 bits registers!
>
> In Intel case a simple doubling of width would work, but they decided that also
> going to PRF would be more benefical, as they decided about the uop cahce, etc.
So it was not free or very easy, was it?
>
> > Words to that effect. I was paraphrasing.
>
> You were puting words in my month.
That's essentially what you said.
>
> > No, I'm asking you.
>
> And I answeared you, but you ignored the answear.
"Ask Intel" is not an answer.
>
> > No, you can have a memory latency benchmark which fits in L4. Or a particular workload which just manages
> > to fit.
>
> And why those wouldn't fit L3?
Because it is smaller than the L4.
>
> > No, why should I? Do you have any die shots for your assertion that it is free or very cheap?
>
> You said A15 FPU were expensive, not me, stop putig words in my month.
You said they were cheap first. So let's see your evidence first.
>
> > But you said that designers and consumers prefer to pay for things which are
> > not relevant to their workloads.
>
> I said two things, you ignored one and are pushing the other to insane levels
No, I didn't ignore anything.
>
> > If high FLOPS is one of those things, moving
> > to a GPU-like core would be a cheap way to win useless benchmarks.
>
> Or just use GPUs, BTW, winning useless bennchmarks is nice, paying to win
> them are not, why don't you re-read the other half of my original post?
>
> Forgot it, you won't read, you are just a useless troll.
>
"designing a FPU that doesn't sucks very badly doesn't look as hard as designing a scheduller that performs exceptioanlly well"
Does not explain anything. It is a completely useless statement. Designing a big L4 cache is not as hard either, but most CPUs don't do that.
> anon (anon.delete@this.anon.com) on July 1, 2013 12:32 am wrote:
> > None of your post provided any other real evidence or logic.
>
> Maybe bacause you do not understand math...
You did not present any math.
>
> > Intel doubled SIMD width in SandyBridge and had to redesign the pipeline to be PRF-based.
> >
> > So you think going to a PRF was pretty easy change?
>
> First, Intel didn't had to go PRF, they choose to go this way, AMD went PRF
> even without 256 bits registers, hell, AMD went PRF with 64 bits registers!
>
> In Intel case a simple doubling of width would work, but they decided that also
> going to PRF would be more benefical, as they decided about the uop cahce, etc.
So it was not free or very easy, was it?
>
> > Words to that effect. I was paraphrasing.
>
> You were puting words in my month.
That's essentially what you said.
>
> > No, I'm asking you.
>
> And I answeared you, but you ignored the answear.
"Ask Intel" is not an answer.
>
> > No, you can have a memory latency benchmark which fits in L4. Or a particular workload which just manages
> > to fit.
>
> And why those wouldn't fit L3?
Because it is smaller than the L4.
>
> > No, why should I? Do you have any die shots for your assertion that it is free or very cheap?
>
> You said A15 FPU were expensive, not me, stop putig words in my month.
You said they were cheap first. So let's see your evidence first.
>
> > But you said that designers and consumers prefer to pay for things which are
> > not relevant to their workloads.
>
> I said two things, you ignored one and are pushing the other to insane levels
No, I didn't ignore anything.
>
> > If high FLOPS is one of those things, moving
> > to a GPU-like core would be a cheap way to win useless benchmarks.
>
> Or just use GPUs, BTW, winning useless bennchmarks is nice, paying to win
> them are not, why don't you re-read the other half of my original post?
>
> Forgot it, you won't read, you are just a useless troll.
>
"designing a FPU that doesn't sucks very badly doesn't look as hard as designing a scheduller that performs exceptioanlly well"
Does not explain anything. It is a completely useless statement. Designing a big L4 cache is not as hard either, but most CPUs don't do that.
